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| INTEGRATED CIRCUITS DATA SHEET P90CE201 16-bit microcontroller Product specification File under Integrated Circuits, IC21 August 1993 Philips Semiconductors Product specification 16-bit microcontroller CONTENTS 1 2 3 4 4.1 4.2 5 5.1 5.2 5.3 5.4 5.5 5.6 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 8 8.1 8.2 9 9.1 9.2 9.3 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION PINNING INFORMATION Pinning Pin description CPU FUNCTIONAL DESCRIPTION General 5.2 Programming model and data organization Internal and external operation Processing states and exception processing Stack format CPU interrupt processing SYSTEM CONTROL Memory mapping Interrupt controller System Control Registers Reset Clock circuitry INSTRUCTION SET Addressing modes Instruction timing I2C-BUS INTERFACE General I2C-bus interface registers UART SERIAL INTERFACE General Operating modes UART registers 10 10.1 11 11.1 12 13 13.1 13.2 13.3 14 15 15.1 15.2 15.3 16 17 18 18.1 18.2 18.3 18.4 19 20 21 8-BIT GENERAL PORT 8-bit General Port registers 8-BIT AUXILIARY PORT 8-bit Auxiliary Port registers WATCHDOG TIMER TIMERS General Timer operating modes Timer registers P90CE201 ELECTROMAGNETIC COMPATIBILITY (EMC) IMPROVEMENTS ELECTRICAL SPECIFICATIONS Limiting values DC Characteristics AC Characteristics REGISTER MAP PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS August 1993 2 Philips Semiconductors Product specification 16-bit microcontroller 1 FEATURES 2 GENERAL DESCRIPTION P90CE201 * CMOS technology * Full 68000 software compatibility * 32-bit internal structure * 16-bit internal data transfer * 8-bit access to external ROM/RAM * External addressing range 16 Mbytes for ROM and 16 Mbytes for RAM * Unused address pins can be used as quasi-bidirectional ports * On-chip address decoder for ROM/RAM * 8 edge triggered programmable interrupts that can also be used as quasi-bidirectional ports * Reset control * Built-in clock generator * 2 fully independent fast I2C-bus serial interfaces * UART serial interface (4 modes) * 3 fully independent 16-bit timers * Watchdog timer * 8-bit quasi-bidirectional port, 4-bits with high drive capability * EMC optimized layout and pinning * 64-pin QFP package The P90CE201 is a member of the P9XCXXX family of highly integrated 16-bit microcontrollers for use in a wide variety of applications. It is fully software compatible with the 68070/68000. The complete set of system functions available on the chip results in reduced system cost. Additionally, its modular design concept permits future extension to the family. 3 ORDERING INFORMATION EXTENDED TYPE NUMBER P90CE201AEB PACKAGE PINS 64 PIN POSITION MATERIAL QFP plastic CODE SOT319(1) CLOCK FREQUENCY (MHz) 24.0 TEMPERATURE RANGE (C) -25 to 85 Note 1. SOT319-2; 1996 November 28. August 1993 3 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 GP0-GP7 (1) CSRAMN CSROMN A0-A15 A16-A23 D0-D7 R/WN PORT ADDRESS DECODER ADDRESS BUFFER DATA INTERFACE OCD (15 : 0) TIMER 0 CPU T0 TIMER 1 SYSTEM CONTROL OCA (31 : 0) TIMER 2 WATCHDOG TIMER T2 TXD UART RESET XTAL1 XTAL2 RESET LOGIC RXD CLOCK I 2C 1 INTN0 INTN7 INTERRUPT CONTROLLER SCL2 I 2C 2 SDA2 MLB015 1. The General Port lines GP5, GP6 and GP7 have alternate functions for Timer 1, SCL1 and SDA1 respectively; see Table 1. Fig.1 Block diagram August 1993 4 Philips Semiconductors Product specification 16-bit microcontroller 4 4.1 PINNING INFORMATION Pinning P90CE201 63 LP7/INTN7 62 LP6/INTN6 61 LP5/INTN5 60 LP4/INTN4 59 LP3/INTN3 58 LP2/INTN2 57 LP1/INTN1 56 LP0/INTN0 53 RESET handbook, full pagewidth 52 VDD2 51 V SS2 50 CSRAMN 49 D3 48 D2 47 D4 46 D1 45 D5 44 D0 43 D6 42 A0 41 D7 40 A1 39 A2 38 A10 37 A3 36 CSROMN 35 A4 34 A11 33 A5 A9 32 64 TXD 55 T2 A7 29 RXD 1 SDA2 2 SCL2 3 GP7/SDA1 4 GP6/SCL1 5 GP0 6 GP1 7 GP2 8 GP3 9 GP4 10 GP5/T1 11 A23/AP7 12 A22/AP6 13 A21/AP5 14 A20/AP4 15 XTAL2 16 XTAL1 17 V DD1 18 V SS1 19 R/WN 20 A19/AP3 21 A18/AP2 22 A16/AP0 23 A17/AP1 24 A15 25 A14 26 A12 27 A13 28 A8 30 A6 31 P90CE201 54 T0 MLB003 Fig.2 Pin configuration for QFP64. August 1993 5 Philips Semiconductors Product specification 16-bit microcontroller 4.2 Pin description QFP64 package. TYPE I/O I/O I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 to 15, 21, 22, 24, 23 25, 26, 28, 27, 34, 38, 32, 30, 29, 31, 33, 35, 37, 39, 40, 42 16 17 18 19 20 36 44, 46, 48, 49, 47, 45, 43, 41 50 51 52 53 54 55 PIN NO. FUNCTION P90CE201 Table 1 MNEMONIC RXD SDA2 SCL2 GP7/SDA1 GP6/SCL1 GP0 GP1 GP2 GP3 GP4 GP5/T1 A23/AP7 to A16/AP0 A15 to A0 Receive Data. RXD is the data input for the UART interface. Serial Data 2 (open drain). SDA2 is the data signal for the second I2C-bus serial interface. Serial Clock 2 (open drain). SCL2 is the clock signal for the second I2C-bus serial interface. General Purpose Port (active HIGH, 3-state). The alternative functions are as follows. SCL1 is the clock signal for the first I2C-bus serial interface. SDA1 is the data signal for the first I2C-bus serial interface. T1 is the input pin for Timer 1. I/O Address Bus. Upper 8-bits of the address bus (A23 to A16). The unused address bits can be selected as a quasi-bidirectional port (AP). Address Bus. Lower 16-bits of the address bus. O XTAL2 XTAL1 VDD1 VSS1 R/WN CSROMN D0 to D7 CSRAMN VSS2 VDD2 RESET T0 T2 O I - - O O O O - - I I I Oscillator output. Not connected if an external clock generator is used. Oscillator input. XTAL1 can also be used as an external clock input if an external clock generator is used. Supply voltage. For internal logic, address bus, data bus, RWN, CSRAMN, CSROMN, XTAL1 and XTAL2. Ground. For internal logic, address bus, data bus, RWN, CSRAMN, CSROMN, XTAL1 and XTAL2. Read (active HIGH)/Write (active LOW). This controls the direction of data flow. Chip Select ROM (active LOW). This signal selects external ROM. Data Bus. 8-bit data bus. Chip Select RAM (active LOW). This signal enables external RAM. Ground. For all other periphery pins (quiet port). Supply voltage. For all other periphery pins (quiet port). Reset (active HIGH). Input pin for an external reset. Timer 0. Input pin for cycle and event counting using Timer 0. Timer 2. Input pin for cycle and event counting using Timer 2. August 1993 6 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 MNEMONIC LP0/INTN0 LP1/INTN1 LP2/INTN2 LP3/INTN3 LP4/INTN4 LP5/INTN5 LP6/INTN6 LP7/INTN7 TXD TYPE I/O 56 57 58 59 60 61 62 63 64 PIN NO. FUNCTION Latched Interrupt inputs (active LOW). A LOW level of 1 clock pulse will be stored as a pending interrupt request. Priority levels are programmable. Unused interrupt inputs can be used as a quasi-bidirectional port (LP). O Transmit Data. TXD is the data output for the UART serial interface. August 1993 7 Philips Semiconductors Product specification 16-bit microcontroller 5 5.1 CPU FUNCTIONAL DESCRIPTION General 5.2 P90CE201 5.2 Programming model and data organization The CPU of the P90CE201 is software compatible with the 68000, consequently programs written for the 68000 will run on the P90CE201 unchanged. However, for certain applications the following differences between the processors should be noted: * The initialization of the System Control Registers. * Differences exist in the address error exception processing since the P90CE201 can provide full error recovery. * The timing is different because of the P90CE201's new architecture and technology. The instruction execution timing is completely different for the same reason. The programming model is identical to that of the 68000 and is shown in Fig.3. It contains seventeen 32-bit registers, a 32-bit Program Counter and a 16-bit Status Register. The first eight registers (D0 to D7) are used as data registers for byte, word and long-word operations. The second group of registers (A0 to A6) and the System Stack Pointer (A7) can be used as software stack pointers and base address registers. In addition, these registers can be used for word and long-word address operations. All seventeen registers can be used as Index Registers. The P90CE201 supports 8, 16 and 32-bit integer data, BCD data 32-bit addresses. Each data type is arranged in memory as shown in Fig.4. 31 handbook, full pagewidth 16 15 8 7 0 DO D1 D2 D3 Eight Data D4 Registers D5 D6 D7 31 16 15 0 A0 A1 A2 Seven A3 Address Registers A4 A5 A6 USER STACK POINTER SUPERVISOR STACK POINTER 31 0 A7 Two Stack Pointers Program Counter 15 SYSTEM BYTE 87 USER BYTE 0 Status Register MCD504 Fig.3 Programming model. August 1993 8 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 bit 7 6 5 4 3 2 1 0 (a) Bit data (1 Byte = 8 bits). bit 15 14 13 12 11 10 MSB BYTE 0 BYTE 2 9 8 LSB 7 6 5 4 3 2 1 0 BYTE 1 BYTE 3 (b) Integer data (1 Byte = 8 bits). bit 15 14 13 12 11 10 MSB 9 8 7 6 5 4 3 2 1 0 LSB WORD 0 WORD 1 WORD 2 (c) Word data (16 bits). bit 15 14 13 12 11 10 MSB LONG WORD 0 9 8 7 6 5 4 3 2 1 0 HIGH ORDER LOW ORDER HIGH ORDER LOW ORDER HIGH ORDER LONG WORD 2 LOW ORDER LSB LONG WORD 1 (d) Long-word data (32 bits). bit 15 14 13 12 11 10 MSB 9 8 7 6 5 4 3 2 1 0 ADDRESS 0 HIGH ORDER LOW ORDER LSB ADDRESS 1 HIGH ORDER LOW ORDER HIGH ORDER ADDRESS 2 LOW ORDER (e) Addresses (1 address =32 bits). bit 15 14 13 12 11 10 MSB BCD 0 BCD 4 BCD 1 BCD 5 9 8 LSB 7 6 5 4 3 2 BCD 3 BCD 7 1 0 BCD 2 BCD 6 (f) BCD data (2 BCD digits = 1 Byte). MCD505 Fig.4 Memory data organization. August 1993 9 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 handbook, full pagewidth BIT 15 T - 13 S - - 10 8 - - - 4 X N Z V 0 C 12 11 10 Trace Mode Supervisor State Interrupt Mask Carry Overflow Zero Negative Extend MCD506 Fig.5 Status Register. 5.3 Internal and external operation The P90CE201 operates with an internal clock frequency of half the oscillator frequency (fOSC/2). Each internal clock cycle is divided into 2 states. A non-access machine cycle has 3 clock cycles or 6 states (S0 to S5). A minimum bus cycle normally consists of 3 clock cycles (6 states). When data transfer has not yet been terminated, wait states (SW) are inserted in multiples of 2. For external memory access, 2 wait states (bus states SB) are added automatically. 5.4 Processing states and exception processing The halted processing state is an indication of a catastrophic hardware failure. For example, if during exception processing of a bus error another bus error occurs, the CPU assumes that the system is unusable and halts. Only an external reset can restart a halted processor. Note that a CPU in the stopped state is not in the halted state or vice versa. The processor can work in the "user" or "supervisor" state determined by the state of the S-bit in the Status Register. Accesses to the on-chip peripherals are achieved in the supervisor state. All exception processing is performed in the supervisor state once the current content of the Status Register has been copied. The exception vector number is then determined and copies of the Status Register, the Program Counter value and the format/vector number are saved on the supervisor stack using the Supervisor Stack Pointer. Finally, the contents of the exception vector location is fetched and loaded into the Program Counter. The CPU is always in one of three processing states: normal, exception or halted. The normal processing state is that associated with instruction execution; the memory references are to fetch instructions and operands and to store results. A special case of the normal state is the stopped state which the processor enters when a STOP instruction is executed. In this state the CPU makes no further memory references. The exception processing state is associated with interrupts, trap instructions, tracing and other exceptional conditions. The exception may be generated internally by an instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt or a reset. August 1993 10 Philips Semiconductors Product specification 16-bit microcontroller 5.4.1 EXCEPTION VECTORS P90CE201 Exception vectors are memory locations from which the CPU fetches the address of a routine that will handle that exception. All exception vectors are 2 words long (see Fig.6) except for the reset vector which is made up of 4 words, containing the Program Counter (PC) and the Supervisor Stack Pointer (SSP). All exception vectors are contained in the supervisor data space. A vector number is an 8-bit number that, when multiplied by 4, gives the address of an exception vector. Vector numbers are generated internally. The memory map for the exception vectors is given in Table 2. handbook, halfpage Word 0 Word 1 NEW PROGRAM COUNTER (HIGH) NEW PROGRAM COUNTER (LOW) MCD509 Fig.6 Exception vector format. August 1993 11 Philips Semiconductors Product specification 16-bit microcontroller Table 2 Exception vector assignment. DEC 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 - 92 96 100 104 108 112 116 120 124 128 - 188 192 - 252 256 - 1020 000 004 008 00C 010 014 018 01C 020 024 028 02C 030 034 038 03C 040 - 05C 060 064 068 06C 070 074 078 07C 080 - 0BC 0C0 - 0FC 100 - 3FC HEX Reset: initial SSP Reset: initial PC Bus error Address error Illegal instruction Zero divide CHK instruction TRAPV instruction Privilege violation Trace Line 1010 emulator Line 1111 emulator Unassigned, reserved Unassigned, reserved Format error Uninitialized interrupt vector Unassigned, reserved Spurious interrupt Level 1 on-chip interrupt autovector Level 2 on-chip interrupt autovector Level 3 on-chip interrupt autovector Level 4 on-chip interrupt autovector Level 5 on-chip interrupt autovector Level 6 on-chip interrupt autovector Level 7 on-chip interrupt autovector TRAP instruction vectors Unassigned, reserved User interrupt vectors ASSIGNMENT P90CE201 VECTOR NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 (note 1) 14 15 16 to 23 (note 1) 24 25 26 27 28 29 30 31 32 to 47 48 to 63 (note 1) 64 to 255 Note 1. Vectors 12, 13, 16 to 23 and 48 to 63 are reserved for future enhancements. No user peripheral devices should be assigned to these numbers. August 1993 12 Philips Semiconductors Product specification 16-bit microcontroller 5.4.2 MULTIPLE EXCEPTIONS * STOP * RESET * RTE * MOVE TO SR * AND (word) immediate to SR * EOR (word) immediate to SR * OR (word) immediate to SR * MOVE USP. 5.4.6 TRACING P90CE201 As two or more exceptions can occur simultaneously, exceptions are grouped in order of priority; as is shown in Table 3. 5.4.3 INSTRUCTION TRAPS Traps are exceptions caused by instructions arising either from CPU recognition of abnormal conditions during instruction execution or from instructions whose normal behaviour is to cause traps. Some instructions are used specifically to generate traps. The TRAP instruction always forces an exception, and is useful for implementing system calls for user programs. The TRAPV and CHK instructions force an exception if the user program detects a run-time error, possibly an arithmetic overflow or a subscript out of bounds. The signed divide (DIVS) and unsigned divide (DIVU) instructions will force an exception if a divide-by-zero operation is attempted. 5.4.4 ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS The CPU includes a facility to trace instructions one by one to assist in program development. In the trace state, after each instruction is executed, an exception is forced so that a debugging program can monitor execution of the program under test. The trace facility uses the T-bit in the supervisor part of the Status Register. If the T-bit is cleared, tracing is disabled and instructions execute normally. If the T-bit is set at the beginning of the execution of an instruction, a trace exception will be generated after that instruction is executed. If the instruction is not executed, either because of an interrupt, or because the instruction is illegal or privileged, the trace exception does not occur. Also, the trace exception does not occur if the instruction is aborted by a reset, bus error, or address error exception. If the instruction is executed and an interrupt is pending, the trace exception is processed before the interrupt. If the execution of an instruction forces an exception, the forced exception is processed before the trace exception. As an extreme illustration of the above rules, consider the arrival of an interrupt during the execution of a TRAP instruction while tracing is enabled. First the trap exception is processed, then the trace exception, and finally the interrupt is processed. Instruction execution resumes in the interrupt handling routine. Illegal instruction is the term used to refer to any word that is not the first word of a legal instruction. During instruction execution, if such an instruction is fetched, an illegal instruction exception occurs. Words with bits 15 to 12 equal to 1010 or 1111 are defined as unimplemented instructions and separate exception vectors are allocated to these patterns for efficient emulation. This facility allows the operating system to detect program errors, or to emulate unimplemented instructions in software. 5.4.5 PRIVILEGE VIOLATIONS To provide system security, various instructions are privileged and any attempt to execute one of the privileged and any attempt to execute one of the privileged instructions while the CPU is in the user state causes an exception. The privileged instructions are: Table 3 Exception grouping and priority. EXCEPTION RESET, ADDRESS ERROR BUS ERROR TRACE, INTERRUPT, ILLEGAL, PRIVILEGE TRAP, TRAPV, CHK, ZERO, DIVIDE, FORMAT ERROR PROCESSING Exception processing begins at the next machine cycle. Exception processing begins before the next instruction. Exception processing is started through normal instruction execution. GROUP 0 1 2 August 1993 13 Philips Semiconductors Product specification 16-bit microcontroller 5.5 Stack format P90CE201 The stack format for exception processing is similar to the 68010 (rather than the 68000) although the information stored is not the same due to the different architecture. To handle this format the P90CE201 differs from the 68000 in that: * The stack format has changed. * The minimum number of words put into, or restored from, the stack is 4 (68010 compatible; not 3 as with the 68000). * The RTE instruction decides (with the aid of the 4 format bits) whether or not more information has to be restored. The P90CE201 long format is used for bus error and address error exceptions; all other exceptions use the short format. * If another format code, other than one of the two listed above, is detected during the restore action, a Format Error occurs. If the user wants to finish the instruction in which the bus or address error occurred, the P90CE201 format must be used on RTE. If no changes to the stack are required during exception processing, the stack format is transparent to the user. 5.5.1 LONG AND SHORT STACK FORMATS SR PCH/PCL handbook, 4 columns SP Status Register. Program Counter High/Low Word. Indicating either a short stack (only the first 4 words), or the long stack format for bus and address error exceptions. See Fig.9. SR PCH PCL FORMAT (4 bits) VECTOR NUMBER SSW MM INTERNAL INFORMATION INTERNAL INFORMATION Short Stack Format FORMAT VECTOR NUMBER The vector number of the exception in the vector table; e.g. 2 for a bus error and 3 for an address error. See Fig.9. SSW MM TDPH/TDPL Special Status Word; see Fig.8. Current Move Multiple Mask. In the event of a faulty write cycle, the data can be found here. The address used during the faulty bus cycle. Data that has been read prior to the faulty cycle can in some cases be found here. Holds the current instruction being executed. Holds either the present instruction being executed or the prefetched instruction. Long Stack Format TPDH TPDL TPFH TPFL DBINH DBINL IR IRC INTERNAL INFORMATION MCD512 TPFH/TPFL DBINH/DBINL IR IRC Fig.7 Stack format. August 1993 14 Philips Semiconductors Product specification 16-bit microcontroller 5.5.2 THE SPECIAL STATUS WORD (SSW) P90CE201 handbook, full pagewidth bit 15 RR 14 * 13 IF 12 11 10 9 8 7 6 5 * 4 * 3 * 2 FC 2 1 FC 1 0 FC 0 DF RM HB BY RW HW LC MCD513 Fig.8 Special Status Word. Table 4 Description of SSW. BIT SSW.15 SSW.14 SSW.13 SSW.12 SSW.11 SSW.10 SSW.9 SSW.8 SSW.7 SSW.6 SSW.5 SSW.4 SSW.3 SSW.2 SSW.1 SSW.0 FUNCTION Rerun. By default this bit is a logic 0. If set to a logic 1, the CPU will not re-run the faulty bus cycle on return from exception (RTE). Undefined, reserved The faulty cycle was an instruction fetch. The faulty cycle was a data fetch. The error occurred during a read-modify-write cycle. High Byte The faulty cycle was a byte transfer. Read/Write cycle High Word The faulty cycle was during a long-word access. Undefined, reserved Undefined, reserved Undefined, reserved Function Code. These three bits hold the internal function code during the faulty bus cycle. The function codes are the same as for the 68000 and affect the status of the CPU during the faulty bus cycle. See Table 5. SYMBOL RR - IF DF RM HB BY RW HW LC - - - FC2 FC1 FC0 Table 5 Internal function codes. FC2 0 0 0 0 1 1 1 1 FC1 0 0 1 1 0 0 1 1 FC0 0 1 0 1 0 1 0 1 Reserved User data User program Reserved Reserved Supervisor data Supervisor program Interrupt acknowledge ADDRESS SPACE August 1993 15 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 bit 15 14 13 12 11 10 FORMAT CODE FORMAT CODE either 0000 or 1111 0 0 9 8 7 6 5 4 3 2 1 0 0 0 VECTOR NUMBER INFORMATION STACKED Short Format (4 words) 68070 Format (17 words) MCD514 Fig.9 Vector number and format code. 5.6 CPU interrupt processing An Interrupt Controller handles all interrupts, solves any priority problems and passes the highest level interrupt to the CPU. The general interrupt handling mechanism and the Interrupt Controller are described in section 6.2. The CPU interrupt handling follows the same basic rules as in the 68000. However, the following changes have been made to simplify system development: * Interrupts with a priority level equal to or less than the priority level actually running will not be accepted. * During the acknowledge cycle of an interrupt, the IPL bits of the Status Register are set to the priority level of the acknowledged interrupt. An exception to this is when the IM bit in SYSCON2 is a logic 0. In this case level 7 is loaded into the Status Register. See section 6.1.2. If the priority of the interrupt pending is greater than the current processor priority then: * The exception processing sequence is started. * A copy of the Status Register is saved. * The privilege level is set to supervisor state. * Tracing is suppressed. * The priority level of the processor is set to that of the interrupt being acknowledged. The processor then gets the vector number from the interrupting device, classifies it as an interrupt acknowledge, and displays the interrupt level number being acknowledged on the address bus. If autovectoring is requested by the interrupting device, the processor internally generates a vector number that corresponds to the interrupt level number. The processor then starts normal exception processing by saving the format word, Program Counter, and Status Register in the supervisor stack. The value of the vector in the format word is either supplied externally by the requesting device or is an internally generated vector number multiplied by four (format is all zeros). The Program Counter value is the address of the instruction that would have been executed if the interrupt had not been present. Then the interrupt vector contents are fetched and loaded into the Program Counter. The interrupt handling routine starts with normal instruction execution. Priority level 7 is a special case; it can only be detected if the priority level was set to a lower value in between. August 1993 16 Philips Semiconductors Product specification 16-bit microcontroller 6 6.1 SYSTEM CONTROL Memory mapping P90CE201 * Maximum flexibility for RAM and ROM sizes. * The full physical memory size can be used without any restrictions. * The minimum number of address pins are used. The validity of data is signalled to the CPU by the internal signal DTACKN. This signal is generated internally after a programmable delay (wait states). By programming the number of wait cycles the user can adapt the program execution times to his memory access times. After reset the delay for the DTACKN signal is set to its maximum value. Programming the number of wait cycles is described in section 6.3.2. The P90CE201 accesses the external ROM and RAM via 8 data lines and up to 24 address lines. Data access to or from the memories is bytewise. The data will be split or restructured internally to match the internal 16-bit data format. The upper byte (bits 15 to 8) of the data is taken from the even address, the lower byte (bits 7 to 0) from the odd address (MSB address + 1). For external memory control the device provides the R/WN signal together with chip enable signals for ROM (CSROMN) and RAM (CSRAMN). CSROMN is activated in the internal address range 0H to FFFFFFH. The CSRAMN signal is activated in the internal address range 1000000H to 1FFFFFFH. In the external world RAM and ROM are wired in parallel with a maximum address range of 16 Mbytes each. If the larger memory of RAM or ROM is smaller than 16 Mbytes the unused address pins can be used as port pins. The advantages of this addressing scheme are: handbook, full pagewidth S0 S1 S2 S3 SB SB S4 S5 S0 S1 S2 S3 SB SB S4 S5 S0 S1 PHI1 A0 A23 D0 D7 R/WN CSRxMN (Additional Wait States) byte write byte read MLB004 Fig.10 External memory interface timing - Word access. August 1993 17 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 handbook, full pagewidth S0 S1 S2 S3 SB SB S4 S5 S0 S1 S2 S3 SB SB S4 S5 S0 S1 PHI1 A0 A23 D0 D7 R/WN CSRxMN (Additional Wait States) byte write byte read MLB005 Fig.11 External memory interface timing - Byte access. August 1993 18 Philips Semiconductors Product specification 16-bit microcontroller 6.2 Interrupt controller P90CE201 The execution of interrupt routines may be interrupted by another higher priority level interrupt request (nested interrupts). In the 68070 mode (SYSCON2.7 = 1), when an interrupt is serviced by the CPU, the corresponding level is loaded into the Status Register. This prevents the current interrupt from getting interrupted by another interrupt request with the same or lower priority level. If SYSCON2.7 = 0, priority level 7 will always be loaded into the Status Register and therefore the current interrupt cannot be interrupted by any other interrupt request. 6.2.2 ACKNOWLEDGE AND INTERRUPT VECTORS An interrupt controller handles all internal and external interrupts. It passes the interrupt with the highest level priority to the CPU. The following interrupt requests are generated by the on-chip peripherals. * I2C1 * I2C2 * UART receiver * UART transmitter * Timer 2 * Timer 1 * Timer 0. The following interrupt requests are sent via external pins. * INTN0 to INTN7 6.2.1 INTERRUPT ARBITRATION When the CPU is ready to service a particular interrupt request, it initiates an "interrupt acknowledge cycle" in order to obtain the interrupt vector from the requesting device. When the device recognizes that its interrupt request has been accepted it either provides an 8-bit interrupt vector together with an internal DTACKN signal (vector mode), or it asserts an internal AVN signal and the interrupt vector is calculated from the interrupt level. 6.2.3 EXTERNAL LATCHED INTERRUPTS The priority level of all interrupts are programmable and each may be allocated a value between 0 and 7. Level 7 has the highest priority, level 0 disables the corresponding interrupt source. In the event of interrupt requests of equal priority level occurring at the same time, then a hardware mechanism gives the following order. * INTN7 * INTN6 * INTN5 * INTN4 * INTN3 * INTN2 * INTN1 * INTN0 * Timer 2 * Timer 1 * Timer 0 * UART receiver * UART transmitter * I2C2 * I2C1. INTN7 to INTN0 are 8 external interrupt inputs; each triggered on the falling edge of the input. Their priority levels as well as their interrupt vectors are programmable. As an alternative function INTN7 to INTN0 may be used as I/O ports. When an interrupt pin is programmed as a port, the corresponding bit in the Port Control Register LPCRH (or LPCRL) is used for port I/O. A read from either of these two registers reads the value from the corresponding bit in the Port Control Register. A read from the Port Pad Control Register LPPH (or LPPL) reads the value from the corresponding port input pin. A write to LPCRH (or LPCRL) or to LPPH (or LPPL) writes the value to the corresponding port register, from where it is driven to the corresponding port pin. The port function is configured as a quasi-bidirectional port. A bit is set to input mode by writing a logic 1 to the corresponding Port Control Register bit. This drives a "weak" logic 1 to the corresponding output pin, which can be overwritten by an external signal. In the following register descriptions "n" represents the external interrupt number (0 to 7), its associated registers are identified using the same number. August 1993 19 Philips Semiconductors Product specification 16-bit microcontroller 6.2.4 LATCHED INTERRUPT REGISTER n (LIRn) bit 7 INTNC1 bit 6 INTNC0 bit 5 AVN bit 4 - bit 3 PIR bit 2 IPL2 bit 1 P90CE201 bit 0 IPL0 IPL1 Fig.12 Latched Interrupt Register n (LIRn). Table 6 Description of LIRn bits. BIT LIRn.7 LIRn.6 LIRn.5 FUNCTION Interrupt Control. These two bits enable/disable the external interrupt INTNn, or select the pin as an I/O port. See Table 7. Autovector. When AVN = 0; INTNn is an autovectored interrupt and the processor calculates the appropriate vector from a fixed vector table. This is also the default value. When AVN = 1; INTNn is a vectored interrupt and the peripheral must provide an 8-bit vector number. Not used; reserved Pending Interrupt Request. If PIR = 1; then a valid interrupt request has been detected. It is automatically reset by the interrupt acknowledge cycle from the CPU. If PIR = 0; there is no pending interrupt request; this is also the default value. PIR can be set or reset by software by writing a logic 1 or logic 0 respectively to PIRn. Interrupt Priority Level. These three bits select the interrupt priority level for the external interrupt INTNn. See Table 8. SYMBOL INTNC1 INTNC0 AVN - PIR LIRn.4 LIRn.3 IPL2 IPL1 IPL0 Table 7 LIRn.2 LIRn.1 LIRn.0 Interrupt INTNn control. INTNC0 0 1 0 1 interrupt enabled Interrupt pin is selected as an I/O port. Reserved INTERRUPT CONTROL Interrupt disabled; this is also the default value. INTNC1 0 0 1 1 Table 8 IPL2 0 0 0 0 1 1 1 1 Selection of interrupt priority level. IPL1 0 0 1 1 0 0 1 1 IPL0 0 1 0 1 0 1 0 1 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 PRIORITY LEVEL Interrupt inhibited; this is also the default value. August 1993 20 Philips Semiconductors Product specification 16-bit microcontroller 6.2.5 LATCHED INTERRUPT VECTOR n (LIVn) bit 7 IV.7 bit 6 IV.6 bit 5 IV.5 bit 4 IV.4 bit 3 IV.3 bit 2 IV.2 bit 1 IV.1 P90CE201 bit 0 IV.0 Fig.13 Latched Interrupt Vector n (LIVn). Table 9 Description of LIVn bits. BIT LIVn.7 to LIVn.0 FUNCTION 8-bit interrupt vector number. The default value of this register is 0FH. SYMBOL IV.7 to IV.0 6.2.6 LATCHED PORT CONTROL REGISTER HIGH (LPCRH) bit 7 INTN7 bit 6 - bit 5 INTN6 bit 4 - bit 3 INTN5 bit 2 - bit 1 INTN4 bit 0 - Fig.14 Latched Port Control Register High (LPCRH). 6.2.7 LATCHED PORT CONTROL REGISTER LOW (LPCRL) bit 7 INTN3 bit 6 - bit 5 INTN2 bit 4 - bit 3 INTN1 bit 2 - bit 1 INTN0 bit 0 - Fig.15 Latched Port Control Register Low (LPCRL). August 1993 21 Philips Semiconductors Product specification 16-bit microcontroller 6.2.8 LATCHED PORT PIN REGISTER HIGH (LPPH) bit 7 INTN7 bit 6 - bit 5 INTN6 bit 4 - bit 3 INTN5 bit 2 - bit 1 P90CE201 bit 0 - INTN4 Fig.16 Latched Port Pin Register High (LPPH). 6.2.9 LATCHED PORT PIN REGISTER LOW (LPPL) bit 7 INTN3 bit 6 - bit 5 INTN2 bit 4 - bit 3 INTN1 bit 2 - bit 1 INTN0 bit 0 - Fig.17 Latched Port Pin Register Low (LPPL). August 1993 22 Philips Semiconductors Product specification 16-bit microcontroller 6.3 System Control Registers P90CE201 The P90CE201 has two System Control Registers SYSCON1 and SYSCON2 which allow system parameters to be selected. 6.3.1 SYSTEM CONTROL REGISTER 1 (SYSCON1) handbook, full pagewidth bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NROD2 NROD1 NROD0 NRAD2 NRAD1 NRAD0 MLB011 Fig.18 System Control Register 1 (SYSCON1). Table 10 Description of SYSCON1 bits. SYMBOL - BIT SYSCON1.15 to SYSCON1.8 SYSCON1.7 SYSCON1.6 SYSCON1.5 SYSCON1.4 SYSCON1.3 SYSCON1.2 SYSCON1.1 SYSCON1.0 These eight bits are not used. FUNCTION NROD2 NROD1 NROD0 - - NRAD2 NRAD1 NRAD0 These three bits select the access time for the ROM area. After a reset operation these bits are logic 0's. See Table 11. not used not used These three bits select the access time for the RAM area. After a reset operation these bits are logic 0's. See Table 11 Table 11 Selection of memory access times for ROM and RAM areas. NROD2 NRAD2 0 0 0 0 Notes 1. 1 internal clock cycle contains 2 wait states. 2. All other states are undefined and reserved. NROD1 NRAD1 0 0 1 1 NROD0 NRAD0 0 1 0 1 ADD WAIT STATES 8 4 2 0 fXTAL (MHz) 24 185 101 60 18 20 235 135 85 35 16 310 185 122 60 12 435 268 185 101 ns ns ns ns UNIT August 1993 23 Philips Semiconductors Product specification 16-bit microcontroller 6.3.2 SYSTEM CONTROL REGISTER 2 (SYSCON2) P90CE201 handbook, full pagewidth bit 15 14 13 12 2 11 2 10 9 8 7 6 5 4 3 2 1 0 I2 C1 TO TOED TOED I C2 I C1 T2 PSBPCLK PSBPCLK IM WD 0 1 0 1 PO PS CON CON SEL T1 T1 PS PO MLB012 Fig.19 System Control Register 2 (SYSCON2). Table 12 Description of SYSCON2 bits. SYMBOL - BIT SYSCON2.15 to SYSCON2.13 SYSCON2.12 These three bits are not used. FUNCTION I2C2CON This bit along with the three bits CR0, CR1 and CR2 held in the Serial Control Register (S2CON), are used to select the bitrate of the I2C-bus 2 interface. If I2C2CON = 0; the interface operates with a high bitrate. If I2C2CON = 1; the interface operates with a low bitrate. This bit along with the three bits CR0, CR1 and CR2 held in the Serial Control Register (S1CON), are used to select the bitrate of the I2C-bus 1 interface. If I2C1CON = 0; the interface operates with a high bitrate. If I2C1CON = 1; the interface operates with a low bitrate. This bit selects the frequency of the clock for Timer 2. If T2SEL = 0; the timer operates at a frequency of fXTAL/2. If T2SEL = 1; the timer operates at a frequency of BPCLK/4. These two bits control the prescaler for the basic peripheral clock. See Table 13. If IM = 0; level 7 is loaded into the Status Register during interrupt processing to prevent the CPU from being interrupted by another interrupt source. If IM = 1; the current interrupt level is loaded into the Status Register allowing nested interrupts. This bit enables or disables the Watchdog timer for bus error (internal) detection. If WD = 0; the timer is disabled. If WD = 1; the timer is enabled for bus error detection. If no acknowledge has been sent by the addressed device after 128 x 16 internal clock cycles the on-chip bus error signal is activated. The state of this bit determines whether general port pins GP.7/SDA1 and GP.6/SCL1 are used as port pins or in their I2C-bus function. When I2C1P0 = 0; the port function is selected. When I2C1P0 = 1; the I2C-bus is selected. This bit enables or disables the prescaler for Timer 0. If T0PS = 0; the prescaler is disabled and the timer operates at a frequency of fXTAL/2. If T0PS = 1; the prescaler is enabled and the timer operates at a frequency of fXTAL/32. These two bits select which transition at the external input will trigger an increment of Timer 0. See Table 14. I2C1CON SYSCON2.11 T2SEL SYSCON2.10 PSBPCLK1 PSBPCLK0 IM SYSCON2.9 SYSCON2.8 SYSCON2.7 WD SYSCON2.6 I2C1PO SYSCON2.5 T0PS SYSCON2.4 T0ED1 T0ED0 SYSCON2.3 SYSCON2.2 August 1993 24 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 SYMBOL T1PS BIT SYSCON2.1 FUNCTION This bit enables or disables the prescaler for Timer 1. If T1PS = 0; the prescaler is disabled and the timer operates at a frequency of fXTAL/2. If T1PS = 1; the prescaler is enabled and the timer operates at a frequency of fXTAL/32. This bit selects whether bit 5 of the general purpose port acts as a port or as an input to Timer 1. If T1PO = 0; bit 5 of the general purpose port acts as a port. If T1PO = 1; bit 5 of the general purpose port acts as an input to Timer 1. T1PO SYSCON2.0 Note 1. All bits of this register have a default value of logic 0 except TOED1 which has a default value of logic 1. Table 13 Selection of basic peripheral clock for BPCLK = 4 MHz. PSBPCLK1 0 0 1 1 PSBPCLK0 0 1 0 1 DIVISOR 3.0 2.5 2.0 1.5 fXTAL (MHz) 24 20 16 12 Table 14 Selection of input trigger for T0. TOED1 0 0 1 1 TOED0 0 1 0 1 Edge detection disabled LOW-to-HIGH transitions will be monitored. HIGH-to-LOW transitions will be monitored. This is the default value after a reset operation. Any transition will be monitored. TRANSITION August 1993 25 Philips Semiconductors Product specification 16-bit microcontroller 6.4 Reset 6.4.3 P90CE201 RESET ACTIVATED BY AN OVERFLOW OF THE WATCHDOG TIMER The reset input for the P90CE201 is RESET (pin 53). A Schmitt trigger is used at the input for noise rejection. The output of the Schmitt trigger is sampled by the reset circuitry every machine cycle. The internal reset circuitry has an additional input which is activated by an overflow of the Watchdog Timer (WDTIM). The On-chip Reset configuration is shown in Fig.20. A global reset may be performed by three different methods: * Applying an external signal to the RESET pin * Automatic Power-on-reset circuitry * Activated by an overflow of the Watchdog Timer. During the reset operation the CPU and peripherals are reset. After an internal start-up time, the CPU reads the reset vectors (the reset vectors are four words long). Address 000000H is loaded into the Supervisor Stack Pointer (SSP), and address 000004H is loaded into the Program Counter (PC). As soon as the SSP and PC have been loaded, the CPU initializes the Status Register to interrupt level 7. Instruction execution then starts at the address indicated by the Program Counter. 6.4.1 EXTERNAL RESET USING THE RESET PIN A reset can also be initiated by an overflow of the Watchdog Timer (see Fig.20). After a reset operation the Watchdog Timer is disabled. Note that when the CPU executes a RESET instruction, the CPU is not affected, only the on-chip peripherals are reset. SCHMITT TRIGGER RESET CIRCUITRY on-chip resistor MLB007 Watchdog timer overflow RESET An external reset is accomplished by applying an external signal to the RESET pin. To ensure that the oscillator is stable before the controller starts, the external signal must be held HIGH for at least 100 ms. 6.4.2 AUTOMATIC POWER-ON RESET V Fig.20 On-chip reset configuration. Providing the rise time of VDD does not exceed 10 ms, an automatic reset can be obtained by connecting the RESET pin to VDD, via a 2.2 F capacitor. When the power is switched on, the voltage on the RESET pin is equal to VDD minus the capacitor voltage, and decreases from VDD as the capacitor charges through the internal resistor (RRESET) to ground. The larger the capacitor, the more slowly VRESET decreases. VRESET must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start-up time, plus 2 machine cycles. The Power-on reset circuitry is shown in Fig.21. DD handbook, halfpage 2.2 F VDD P90CE201 RESET R RESET MLB006 Fig.21 Power-on reset circuitry. August 1993 26 Philips Semiconductors Product specification 16-bit microcontroller 6.5 Clock circuitry P90CE201 The P90CE201 is specified for a maximum crystal frequency of 24 MHz. The internal clock frequency is the crystal frequency (fXTAL) divided by 2. For some peripherals such as the UART and Watchdog Timer, a main prescaler generates a basic peripheral clock. Frequencies other than the basic peripheral clock will be generated within the peripherals. The prescaler is programmed by register SYSCON2. Table 15 shows the frequencies of the basic peripheral clock generated by the main prescaler. The oscillator circuit of the P90CE201 is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuitry. Both are operated in parallel resonance. XTAL1 is the high gain amplifier input, and XTAL2 is the input; see Fig.22. To drive the P90CE201 externally, XTAL1 is driven from an external source and XTAL2 left open-circuit; see Fig.23. Table 15 Basic peripheral clock frequencies. fXTAL (MHz) 24 20 16 12 fINT (MHz) 12 10 8 6 fINT DIVISOR (MHz) 3 4.00 3.33 2.66 2.00 2.5 4.80 4.00 3.20 2.40 2 6.00 5.00 4.00 3.00 1.5 8.00 6.66 5.33 4.00 handbook, halfpage C1 20 pF handbook, halfpage XTAL1 external clock (not TTL compatible) XTAL1 C2 20 pF XTAL2 not connected XTAL2 MLA763 MLA764 Fig.22 Oscillator circuit. Fig.23 Driving from an external source. August 1993 27 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 7 INSTRUCTION SET The P90CE201 is completely code compatible with the 68000. Consequently, programs developed for the 68000 will run on the P90CE201. This applies to both the source and object codes. The instruction set was designed to minimize the number of mnemonics that the programmer has to remember. CONDITION CODES MNEMONIC ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL, ASR BCC BCHG DESCRIPTION OPERATION X Add Decimal with Extend (Destination)10 + (Source)10 + X Destination Add Binary Add Address Add Immediate Add Quick Add Extended AND Logical AND Immediate Arithmetic Shift Branch Conditionally Test a Bit and Change (Destination) + (Source) Destination (Destination) + (Source) Destination (Destination) + Immediate Data Destination (Destination) + Immediate Data Destination (Destination) + (Source) + X Destination (Destination) (Source) Destination (Destination) Immediate Data Destination (Destination) Shifted by < count > Destination If CC then PC + d PC ~(< bit number >) of Destination Z ~(< bit number >) of Destination < bit number > of Destination ~(< bit number >) of Destination Z PC + d PC ~(< bit number >) of Destination Z 1 < bit number > of Destination PC SP @ -; PC + d PC ~(< bit number >) of Destination Z If Dn < 0 or Dn > (< source >) then TRAP 0 Destination (Destination) - (Source) (Destination) - (Source) (Destination) - Immediate Data (Destination) - (Source) If (not CC) then Dn - 1 Dn; if Dn -1 then PC +d PC (Destination) / (Source) Destination (Destination) / (Source) Destination * * - * * * - - * - - N U * - * * * * * * - - Z * * - * * * * * * - * V U * - * * * 0 0 * - - C * * - * * * 0 0 * - - BCLR BRA BSET BSR BTST CHK CLR CMP CMPA CMPI CMPM DBCC DIVS DIVU Test a Bit and Clear Branch Always Test a Bit and Set Branch to Subroutine Test a Bit Check Register against Bounds Clear an Operand Compare Compare Address Compare Immediate Compare Memory Test Condition, Decrement & Branch Signed Divide Unsigned Divide - - - - - - - - - - - - - - - - - - - * 0 * * * * - * * * - * - * U 1 * * * * - * * - - - - - U 0 * * * * - * * - - - - - U 0 * * * * - 0 0 August 1993 28 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 CONDITION CODES MNEMONIC EOR EORI EXG EXT JMP JSR LEA LINK LSL, LSR MOVE MOVE to CCR MOVE to SR MOVE from SR MOVE USP MOVEA MOVEM MOVEP MOVEQ MULS MULU NBCD NEG NEGX NOP DESCRIPTION Exclusive OR Logical Exclusive OR Immediate Exchange Register Sign Extend Jump Jump to Subroutine Load Effective Address Link and Allocate Logical Shift Move Data from Source to Destination Move to Condition Code Move to the Status Register Move from the Status Register Move Address Move Multiple Registers Move Peripheral Data Move Quick Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation OPERATION X (Destination) (Source) Destination (Destination) Immediate Data Destination Rx Ry (Destination) Sign - extended Destination Destination PC PC SP @ - ; Destination PC Destination An An SP @ - ; SP An; SP + d SP (Destination) Shifted by < count > Destination (Source) Destination (Source) CCR (Source) SR SR Destination - - - - - - - - * - * * - - - - - - - - * * * - N * * - * - - - - * * * * - - - - - * * * U * * - Z * * - * - - - - * * * * - - - - - * * * * * * - V 0 0 - 0 - - - - 0 0 * * - - - - - 0 * * U * * - C 0 0 - 0 - - - - * 0 * * - - - - - 0 0 0 * * * - Move User Stack Pointer USP An; An USP (Source) Destination Registers Destination; (Source) Registers (Source) Destination Immediate Data Destination (Destination) * (Source) Destination (Destination) * (Source) Destination 0 - (Destination)10 - X Destination 0 - (Destination) Destination 0 - (Destination) - X Destination - August 1993 29 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 CONDITION CODES MNEMONIC NOT OR ORI PEA RESET ROL, ROR ROXL, ROXR RTE RTR RTS SBCD SCC STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPV TST UNLK Notes 1. [ ] = bit number 2. * = affected 3. - = unaffected 4. 0 = cleared 5. 1 = set 6. U = defined 7. @ = location addressed by DESCRIPTION Logical Complement Inclusive OR Logical Inclusive OR Immediate Push Effective Address Reset External Devices Rotate (Without Extend) Rotate with Extend Return from Exception Return and Restore Condition Codes Return from Subroutine Subtract Decimal with Extend Set According to Condition Load Status Register and Stop Subtract Binary Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Halves OPERATION X ~(Destination) Destination (Destination) v (Source) Destination (Destination) v Immediate Data Destination Destination SP @- - (Destination) Rotated by < count > Destination (Destination) Rotated by < count > Destination SP @ + SR; SP @ + PC SP @ + SR; SP @ + PC SP @ + PC (Destination)10 - (Source)10 - X Destination if CC then 1 Destination; else 0 Destination Immediate Data SR; STOP (Destination) - (Source) Destination (Destination) - (Source) Destination (Destination) - Immediate Data Destination (Destination) - Immediate Data Destination (Destination) - (Source) - X Destination Register [ 31:16 ] Register [ 15:0 ] * * - * - * * - * * * - - - - - - - - - - - - * * * - U - * * - * * * * * - - * - N * * * - - * * * * - * - * * - * * * * * - - * - Z * * * - - * * * * - U - * * - * * * 0 0 - - 0 - V 0 0 0 - - 0 0 * * - * - * * - * * * 0 0 - - 0 - C 0 0 0 - - * * Test and Set an Operand (Destination) Tested CC; 1 [ 7 ] of Destination Trap Trap on Overflow Test and Operand Unlink PC SSP @ - ; SR SSP @ - ; (Vector) PC If V then TRAP (Destination) Tested CC An SP; SP @ + An August 1993 30 Philips Semiconductors Product specification 16-bit microcontroller 7.1 Addressing modes P90CE201 Table 16 Data addressing modes. MODE Register Direct Addressing Data Register Direct Address Register Direct Absolute Data Addressing Absolute Short Absolute Long Program Counter Relative Addressing Relative with Offset Relative with Index and Offset Register Indirect Addressing Register Indirect Postincrement Register Indirect Predecrement Register Indirect Register Indirect with Offset Indexed Register Indirect with Offset Immediate Data Addressing Immediate Quick Immediate Implied Addressing Implied Register Notes 1. EA = Effective Address 2. An = Address Register 3. Dn = Data Register 4. Xn = Address or Data Register used as Index Register 5. N = 1 for bytes; 2 for words; 4 for long words 6. = Replaces 7. SR = Status Register 8. PC = Program Counter 9. () = Contents of 10. d8 = 8-bit offset (displacement) 11. d16 = 16-bit offset (displacement) 12. SP = Stack Pointer 13. SSP = System Stack Pointer 14. USP = User Stack Pointer EA = SR, USP, SSP, PC, SP DATA = Next Word(s) Inherent Data EA = (An) EA = (An), An An + N An An - N, EA = (An) EA = (An) + d16 EA = (An) + (Xn) + d8 EA = (PC) + d16 EA = (PC) + (Xn) + d8 EA = (Next Words) EA = (Next Two Words) EA = Dn EA = An GENERATION August 1993 31 Philips Semiconductors Product specification 16-bit microcontroller 7.2 Instruction timing P90CE201 This data assumes that both memory read and write cycle times are four internal clock periods (no additional wait states). Additional wait states for memory accesses have to be added to the total instruction time. Accesses to registers listed in the Register Map are only three clock periods, therefore one clock period can be subtracted for each access to such a register. However, access to the UART registers takes up to ten clock periods due to synchronization. Consequently, ten clock periods have to be added for UART register accesses. Table 17 Effective address calculation times. SOURCE Rn (An) (An)+ -(An) d(An) d(An, Xi) xxx.S xxx.L d(PC) d(PC, Xi) #xxx Note 1. The number of bus read and write cycles are shown in parentheses as (R/W). Table 18 MOVE Byte and Move Word instruction clock periods. SOURCE Rn (An) (An)+ -(An) d(An) d(An,Xi) xxx.S xxx.L d(PC) d(PC,Xi) #xxx 7 11 11 14 18 21 15 19 18 21 11 Rn (1/0) 11 (2/0) 15 (2/0) 15 (2/0) 18 (3/0) 22 (3/0) 25 (3/0) 19 (4/0) 23 (3/0) 22 (3/0) 25 (2/0) 15 (An) (1/1) 11 (2/1) 15 (2/1) 15 (2/1) 18 (3/1) 22 (3/1) 25 (3/1) 19 (4/1) 23 (3/1) 22 (3/1) 25 (2/1) 15 (An)+ (1/1) 14 (2/1) 18 (2/1) 18 (2/1) 22 (3/1) 25 (3/1) 28 (3/1) 22 (4/1) 26 (3/1) 25 (3/1) 28 (2/1) 18 -(An) (1/1) 18 (2/1) 22 (2/1) 22 (2/1) 25 (3/1) 29 (3/1) 32 (3/1) 26 (4/1) 30 (3/1) 29 (3/1) 32 (2/1) 22 d(An) d(An,Xi) (1/1) 15 (2/1) 19 (2/1) 19 (2/1) 22 (3/1) 26 (3/1) 29 (3/1) 23 (4/1) 27 (3/1) 26 (3/1) 29 (2/1) 19 xxx.S (1/1) 19 (2/1) 23 (2/1) 23 (2/1) 26 (3/1) 30 (3/1) 33 (3/1) 27 (4/1) 31 (3/1) 30 (3/1) 33 (2/1) 23 xxx.L (1/1) (2/1) (2/1) (2/1) (3/1) (3/1) (3/1) (4/1) (3/1) (3/1) (2/1) ADDRESSING MODE Data Address Register Direct Address Register Indirect Address Register Indirect postincrement Address Register Indirect predecrement Address Register Indirect Displacement Address Register Indirect with Index Absolute Short Absolute Long Program Counter with Displacement Program Counter with Index Immediate BYTE, WORD 0 4 4 7 11 14 8 12 11 14 4 (0/0) (1/0) (1/0) (1/0) (2/0) (2/0) (2/0) (3/0) (2/0) (2/0) (1/0) 0 8 8 11 15 18 12 16 15 18 8 LONG (0/0) (2/0) (2/0) (2/0) (3/0) (3/0) (3/0) (4/0) (3/0) (3/0) (2/0) (1/1) 21 (2/1) 25 (2/1) 25 (2/1) 28 (3/1) 32 (3/1) 35 (3/1) 29 (4/1) 33 (3/1) 32 (3/1) 35 (2/1) 25 August 1993 32 Philips Semiconductors Product specification 16-bit microcontroller Table 19 MOVE Long instruction clock periods. SOURCE Rn (An) (An)+ -(An) d(An) d(An,Xi) xxx.S xxx.L d(PC) d(PC,Xi) #xxx 7 15 15 18 22 25 19 23 22 25 15 Rn (1/0) 15 (3/0) 23 (3/0) 23 (3/0) 26 (4/0) 30 (4/0) 33 (4/0) 27 (5/0) 31 (4/0) 30 (4/0) 33 (3/0) 23 (An) (1/2) 15 (3/2) 23 (3/2) 23 (3/2) 26 (4/2) 30 (4/2) 33 (4/2) 27 (5/2) 31 (4/2) 30 (4/2) 33 (3/2) 23 (An)+ (1/2) 18 (3/2) 26 (3/2) 26 (3/2) 29 (4/2) 33 (4/2) 36 (4/2) 30 (5/2) 34 (4/2) 33 (4/2) 36 (3/2) 26 -(An) (1/2) 22 (3/2) 30 (3/2) 30 (3/2) 33 (4/2) 37 (4/2) 40 (4/2) 34 (5/2) 38 (4/2) 37 (4/2) 40 (3/2) 30 d(An) d(An,Xi) (2/2) 19 (4/2) 27 (4/2) 27 (4/2) 30 (5/2) 34 (5/2) 37 (5/2) 31 (6/2) 35 (5/2) 34 (5/2) 37 (4/2) 27 P90CE201 xxx.S (2/2) 23 (4/2) 31 (4/2) 31 (4/2) 34 (5/2) 38 (5/2) 41 (5/2) 35 (6/2) 39 (5/2) 38 (5/2) 41 (4/2) 31 xxx.L (3/2) (5/2) (5/2) (5/2) (6/2) (6/2) (6/2) (7/2) (6/2) (6/2) (5/2) (2/2) 25 (4/2) 33 (4/2) 33 (4/2) 36 (5/2) 40 (5/2) 43 (5/2) 37 (6/2) 41 (5/2) 40 (5/2) 43 (4/2) 33 Table 20 Standard instruction clock periods. INSTR ADD AND CMP DIVS DIVU EOR MULS MULU OR SUB SIZE Byte, Word Long Byte, Word Long Byte, Word Long - - Byte, Word Long - - Byte, Word Long Byte, Word Long Notes 1. + = add effective address calculation time 2. * = the duration of the instruction is constant 3. ** = indicates maximum value. op < ea > ,An 7 + (1/0) 7 + (1/0) - - 7 + (1/0) 7 + (1/0) - - - - - - - - 7 + (1/0) 7 + (1/0) op < ea > ,Dn 7 + (1/0) 7 + (1/0) 7 + (1/0) 7 + (1/0) 7 + (1/0) 7 + (1/0) 169 + 130 + ** * op < Dn > ,M 11 + (1/1) 15 + (1/2) 11 + (1/1) 15 + (1/2) - - - - 11 + (1/1) 15 + (1/2) (1/0) (3) (1/0) (2) 7 + (1/0) 7 + (1/0) 76 + (1/0) * (2) (2) - 11 + (1/1) 15 + (1/2) 11 + (1/1) 15 + (1/2) 76 + (1/0) * 7 + (1/0) 7 + (1/0) 7 + (1/0) 7 + (1/0) August 1993 33 Philips Semiconductors Product specification 16-bit microcontroller Table 21 Immediate instruction clock periods. INSTR. ADDI ADDQ ANDI CMPI EORI MOVEQ ORI SUBI SUBQ SIZE Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Long Byte, Word Long Byte, Word Long Byte, Word Long Note 1. + = add effective calculation time. op < # > ,Dn 14 (2/0) 18 (3/0) 7 (1/0) 7 (1/0) 14 (2/0) 18 (3/0) 14 (2/0) 18 (3/0) 14 (2/0) 18 (3/0) 7 (1/0) 14 (2/0) 18 (3/0) 14 (2/0) 18 (3/0) 7 (1/0) 7 (1/0) op < # > ,An - - 7 (1/0) 7 (1/0) - - - - - - - - - - - 7 (1/0) 7 (1/0) P90CE201 op < # > ,< M > 18 + (2/1) 26 + (3/2) 11 + (1/1) 15 + (1/2) 18 + (2/1) 24 + (3/2) 14 + (2/0) 18 + (3/0) 18 + (2/1) 26 + (3/2) - 18 + (2/1) 26 + (3/2) 18 + (2/1) 26 + (3/2) 11 + (1/1) 15 + (1/2) August 1993 34 Philips Semiconductors Product specification 16-bit microcontroller Table 22 Single operand instruction clock periods. INSTRUCTION CLR NBCD NEG NEGX NOT Scc TAS TST SIZE Byte, Word Long Byte Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Byte, Word Long Notes 1. + = add effective calculation time 2. * = subtract one read cycle (-4(1/0)) from effective address calculation 3. ** = subtract two read cycles (-8(2/0)) from effective address calculation. Table 23 Shift/rotate instruction clock periods. INSTRUCTION ASR,ASL LSR,LSL ROR,ROL ROXR,ROXL SIZE Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Note 1. + = add effective calculation time. REGISTER 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) REGISTER 7 (1/0) 7 (1/0) 10 (1/0) 7 (1/0) 7 (1/0) 7 (1/0) 7 (1/0) 7 (1/0) 7 (1/0) 13 (1/0) 13 (1/0) 10 (1/0) 7 (1/0) 7 (1/0) P90CE201 MEMORY 11 (1/1)+ * (2) 15 (1/2)+ ** (3) 14 (1/1)(2) 11 (1/1)+ 15 (1/2)+ 11 (1/1)+ 15 (1/2)+ 11 (1/1)+ 15 (1/2)+ 17 (1/1)+ 14 (1/1)+ 15 (2/1)+ * (2) 7 (1/0)+ 7 (1/0)+ MEMORY 14 (1/1)+ - 14 (1/1)+ - 14 (1/1)+ - 14 (1/1)+ - August 1993 35 Philips Semiconductors Product specification 16-bit microcontroller Table 24 Bit manipulation instruction clock periods. DYNAMIC INSTRUCTION BCHG BCLR BSET BTST SIZE REGISTER Byte Long Byte Long Byte Long Byte Long Note 1. + = add effective calculation time. Table 25 Conditional instruction clock periods. INSTRUCTION Bcc BRA BSR DBcc CHK TRAPV Note 1. + = add effective calculation time. DISPLACEMENT .B .W .B .W .B .W cc True cc False - - TRAP/BRANCH TAKEN 13 (1/0) 14 (2/0) 13 (1/0) 14 (2/0) 21 (1/2) 25 (2/2) - 17 (2/0) 70 (3/4) 55 (3/4) - 10 (1/0) - 10 (1/0) - 10 (1/0) - 7 (1/0) MEMORY 14 (1/1)+ - 14 (1/1)+ - 14 (1/1)+ - 7 (1/0)+ - REGISTER - 17 (2/0) - 17 (2/0) - 17 (2/0) - 14 (2/0) P90CE201 STATIC MEMORY 21 (2/1)+ - 21 (2/1)+ - 21 (2/1)+ - 14 (2/0)+ - TRAP/BRANCH NOT TAKEN 13 (1/0) 14 (2/0) - - - - 14 (2/0) 17 (3/2) 19 (1/0)+ 10 (1/0) August 1993 36 Philips Semiconductors Product specification 16-bit microcontroller Table 26 JMP, JSR, LEA, PEA, MOVEM instruction clock periods. INSTR JMP JSR LEA PEA MOVEM MR Size - - - - - - - - .W .L 7 (1/0) 18 (1/2) 7 (1/0) 18 (1/2) 26 + 7n (2+n/0) 26 + 11n (2+2n/0) 23 + 7n (2/n) 23 + 11n (2/2N) (An) - - - - - - - - 26 + 7n (2+n/0) (An)+ - - - - - - - - - - -(An) d(An) 14 (2/0) 25 (2/2) 14 (2/0) 25 (2/2) 30 + 7n (3+n/0) 30 + 11n (3+2n/0) 27 + 7n (3/n) 27 + 11n (3/2n) d(An, Xi) 17 (2/0) 28 (2/2) 17 (2/0) 28 (2/2) 33 + 7n (3+n/0) 33 + 11n (3+2n/0) 30 + 7n (3/n) 30 + 11n (3/2n) xxx.S 14 (2/0) 25 (2/2) 14 (2/0) 25 (2/2) 30 + 7n (3+n/0) xxx.L 18 (3/0) 29 (3/2) 18 (3/0) 29 (3/2) 34 + 7n (4+n/0) P90CE201 d(PC) 14 (2/0) 25 (2/2) 14 (2/0) 25 (2/2) 30 + 7n (3+n/0) d(PC,Xi) 17 (2/0) 28 (2/2) 17 (2/0) 28 (2/2) 33 + 7n (3+n/0) 26 + 11n - (2+2n/0) 30 + 11n 34 + 11n 30 + 11n 33 + 11n (3+2n/0) (3+2n/0) (4+2n/0) (3+2n/0) 27 + 7n (3/n) 31 + 7n (4/n) - - - - - - MOVEM RM .W .L - - - - 23 + 7n (2/n) 23 + 11n (2/2n) 27 + 11n 31 + 11n - (3/2n) (4/2n) - Note 1. n = number of registers to move. Table 27 Multi-precision instruction clock periods. INSTRUCTION ADDX CMPM SUBX ABCD SBCD SIZE Byte, Word Long Byte, Word Long Byte, Word Long Byte Byte op Dn, Dn 7 (1/0) 7 (1/0) - - 7 (1/0) 7 (1/0) 10 (1/0) 10 (1/0) op M, M 28 (3/1) 40 (5/2) 18 (3/0) 26 (5/0) 28 (3/1) 40 (5/2) 31 (3/1) 31 (3/1) August 1993 37 Philips Semiconductors Product specification 16-bit microcontroller Table 28 Miscellaneous clock periods. INSTRUCTION ANDI to CCR ANDI to SR EORI to CCR EORI to SR EXG EXT LINK MOVE from SR MOVE to CCR MOVE to SR MOVE from USP MOVE to USP MOVEP NOP ORI to CCR ORI to SR RESET RTE - short format RTE - long format no rerun with rerun return of TAS RTR RTS STOP SWAP UNLK Note 1. + = add effective address calculation time. - - - - - WORD LONG - - - - - - WORD LONG - - - - - - - - - - - - - - 140 146 151 22 15 17 7 15 (18/0) (18/0) (19/0) (4/0) (3/0) (2/0) (1/0) (3/0) SIZE REGISTER 14 14 14 14 13 7 7 25 7 10 10 7 7 - - 7 14 14 154 39 (2/0) (2/0) (2/0) (2/0) (1/0) (1/0) (1/0) (2/2) (1/0) (1/0) (1/0) (1/0) (1/0) - - (1/0) (2/0) (2/0) (1/0) (5/0) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 10 10 (1/1)+ (1/0)+ (1/0)+ MEMORY REGISTER to MEMORY - - - - - - - - - - - - - 25 39 (2/2) (2/4) P90CE201 MEMORY to REGISTER - - - - - - - - - - - - - 22 36 - - - - - - - - - - - - - - (4/0) (6/0) August 1993 38 Philips Semiconductors Product specification 16-bit microcontroller Table 29 Exception processing clock periods. EXCEPTION Address error Interrupt Illegal instruction Privilege instruction Trace Trap Divide by Zero RESET (note 2) Note 1. The interrupt acknowledge bus cycle is assumed to take four clock periods. 2. The maximum time from when RESET is first sampled as released to first instruction fetch. P90CE201 NUMBER OF CLOCK PERIODS 158 (3/17) 65 (4/4), note 1 55 (3/4) 55 (3/4) 55 (3/4) 52 (3/4) 64 (3/4)+ 43 (4/0) August 1993 39 Philips Semiconductors Product specification 16-bit microcontroller 8 8.1 I2C-BUS INTERFACE General P90CE201 The P90CE201 contains two fully independent I2C-bus serial interfaces (I2C1 and I2C2); the functionality of both is identical. The I2C-bus interfaces can operate in four modes: 1. Master transmitter 2. Master receiver 3. Slave transmitter 4. Slave receiver. The I2C-bus interface is connected to the I2C-bus by a data pin (SDA) and by a clock pin (SCL). Data transport, clock generation, address recognition and bus arbitration are all controlled by hardware. Each I2C-bus interface is controlled by a set of six registers. handbook, full pagewidth SLAVE ADDRESS SnADR GC SDAn SnDAT ARBITRATION LOGIC SHIFT REGISTER INTERNAL BUS 0 0 MLB252 SCLn BUS CLOCK GENERATOR 7 SnCON 6 5 4 3 2 1 7 SnSTA 6 5 4 3 2 1 Fig.24 Block diagram of I2C-bus serial interface. August 1993 40 Philips Semiconductors Product specification 16-bit microcontroller 8.2 I2C-bus interface registers P90CE201 In the following register descriptions "n" represents the I2C-bus serial interface number (1 or 2); its associated registers are identified using the same number. 8.2.1 SERIAL CONTROL REGISTER (SnCON) S1CON is located at address 8000 2007H; S2CON is located at address 8000 2017H. These registers have a default value of 00H. bit 7 CR2 bit 6 ENS bit 5 STA bit 4 STO bit 3 SI bit 2 AA bit 1 CR1 bit 0 CR0 Fig.25 Serial Control Register (SnCON) Table 30 Description of SnCON bits. SYMBOL CR2 CR1 CR0 ENS STA BIT SnCON.7 SnCON.1 SnCON.0 SnCON.6 SnCON.5 FUNCTION Clock Rate. These three bits along with bit SYSCON2.12 (or SYSCON2.11) determine the serial clock frequency that is generated in the master mode of operation. The frequencies of 100 kHz and 400 kHz can be selected for the oscillators frequencies of 12, 16, 20 and 24 MHz, as shown in Table 31. Enable Serial I/O. When ENS = 0; the serial interface I/O is disabled and reset. When ENS = 1; the serial interface is enabled. Start flag. When this bit is set in slave mode, the hardware checks the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in Master Mode it will generate a repeated START condition. Stop flag. If this bit is set in the master mode a STOP condition is generated. A STOP condition detected on the I2C-bus clears this bit. The STOP bit may also be set in Slave Mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C-bus, but the hardware releases the SDA and SCL lines and switches to the not selected slave receiver mode. The STOP flag is cleared by the hardware. Serial Interrupt flag. This flag is set, and an interrupt is generated, after any of the following events occur: - A START condition is generated in Master Mode - The own slave address has been received during AA = 1 - The general call address has been received while SnADR.0 = 1 and AA = 1 - A data byte has been received or transmitted in master mode - A data byte has been received or transmitted as selected slave - A STOP or START condition is received as selected slave receiver or transmitter. While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset by software. STO SnCON.4 SI SnCON.3 August 1993 41 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 SYMBOL AA BIT SnCON.2 FUNCTION Assert Acknowledge. When this bit is set, an acknowledge is returned after any one of the following conditions: - Own slave address is received - The general call address is received (S1ADR.0 = 1) - A data byte is received, while the device is programmed to be a master receiver - A data byte is received, while the device is a selected slave receiver. When this bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own slave address or general call address is received. Table 31 Selection of I2C-bus bit rate. CR3 (note 1) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note 1. CR3 is defined by SYSCON2.12 (or SYSCON2.11). CR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CR0 12 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 200 240 300 400 50 60 75 100 6.25 7.5 9.38 12.5 3.13 3.75 4.69 6.25 BIT RATE at fCLK (MHz) 16 266.66 320 400 - 66.67 80 100 - 8.33 10 12.5 16.67 4.17 5 6.25 8.33 20 333.33 400 - - 83.33 100 - - 10.42 12.5 15.63 20.83 5.21 6.25 7.81 10.42 24 400 - - - 100 - - - 12.5 15 18.75 25 6.25 7.5 9.38 12.5 kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz Standard I2C-bus Fast I2C-bus UNIT DEVICE August 1993 42 Philips Semiconductors Product specification 16-bit microcontroller 8.2.2 SERIAL STATUS REGISTER (SnSTA) P90CE201 S1STA resides at address 8000 2005H; S2STA resides at address 8000 2015H. The contents of the Serial Status Registers may be used as vectors to service routines. This optimizes the response time of the software and consequently that of the I2C-bus. S1STA and S2STA are read-only registers. These registers have a default value of F8H. bit 7 SC4 bit 6 SC3 bit 5 SC2 bit 4 SC1 bit 3 SC0 bit 2 0 bit 1 0 bit 0 0 Fig.26 Serial Status Register (SnSTA). Table 32 Description of SnSTA bits. SYMBOL SC4 SC3 SC2 SC1 SC0 - - - BIT SnSTA.7 SnSTA.6 SnSTA.5 SnSTA.4 SnSTA.3 S1STA.2 S1STA.1 S1STA.0 FUNCTION Status Code. These 5 bits may be read in order to determine the status of the I2C-bus. Tables 33 to 37 show all the status codes. These three bits are held LOW and allow the user to use the status code directly as a vector to a service routine. Table 33 Master Transmitter Mode. S1STA VALUE 08H 10H 18H 20H 28H 30H 38H DESCRIPTION A START condition has been transmitted A repeated START condition has been transmitted SLA and W have been transmitted, ACK has been received SLA and W have been transmitted, ACK received DATA of SnDAT has been transmitted, ACK received DATA of SnDAT has been transmitted, ACK received Arbitration lost in SLA, R/W or DATA Table 34 Master Receiver Mode. S1STA VALUE 08H 10H 38H 40H 48H 50H 58H DESCRIPTION A START condition has been transmitted A repeated START condition has been transmitted Arbitration lost while returning ACK SLA and R have been transmitted, ACK received SLA and R have been transmitted, ACK received DATA has been received, ACK returned DATA has been received, ACK returned August 1993 43 Philips Semiconductors Product specification 16-bit microcontroller Table 35 Slave Receiver Mode. S1STA VALUE 60H 68H 70H 78H 80H 88H 90H 98H A0H DESCRIPTION Own SLA and W have been received, ACK returned P90CE201 Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned General call has been received, ACK returned Arbitration lost in SLA, R/W as MST. General call received, ACK returned Previously addressed with own SLA. DATA byte received, ACK returned Previously addressed with own SLA. DATA byte received, ACK returned Previously addressed with general call. DATA byte received, ACK has been returned Previously addressed with general call. DATA byte received, ACK has been returned A STOP condition or repeated START condition received while still addressed as SLV/REC or SLV/TRX Table 36 Slave Transmitter Mode. S1STA VALUE A8H B0H B8H C0H C8H DESCRIPTION Own SLA and R received, ACK returned Arbitration lost in SLA, R/W as MST. Own SLA and R received, ACK returned DATA byte has been transmitted, ACK received DATA byte has been transmitted, ACK received Last DATA byte has been transmitted, ACK received Table 37 Miscellaneous. S1STA VALUE 00H F8H ABBREVIATIONS USED: SLA: R: W: ACK: ACK: DATA: MST: SLV: TRX: REC: 7-bit slave address Read bit Write bit Acknowledgement (acknowledge bit = logic 0) No acknowledgement (acknowledge bit = logic 1) 8-bit data byte to or from I2C-bus Master Slave Transmitter Receiver. DESCRIPTION Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition No relevant information available, SI not set August 1993 44 Philips Semiconductors Product specification 16-bit microcontroller 8.2.3 DATA SHIFT REGISTER (SnDAT) P90CE201 S1DAT is located at address 8000 2001H; S2DAT is located at address 8000 2011H. These two identical registers contain the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first; i.e. data shifted from right to left. These registers have a default value of 00H. bit 7 DATA.7 bit 6 DATA.6 bit 5 DATA.5 bit 4 DATA.4 bit 3 DATA.3 bit 2 DATA.2 bit 1 DATA.1 bit 0 DATA.0 Fig.27 Data Shift Register (SnDAT). 8.2.4 ADDRESS REGISTER (SnADR) S1ADR resides at address 8000 2003H; S2ADR resides at address 8000 2013H. These two identical 8-bit registers may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. The LSB (GC) is used to determine whether the general call address is recognized. These registers have a default value of 00H. bit 7 SLA6 bit 6 SLA5 bit 5 SLA4 bit 4 SLA3 bit 3 SLA2 bit 2 SLA1 bit 1 SLA0 bit 0 GC Fig.28 Address Register (SnADR). Table 38 Description of SnADR bits. SYMBOL SLA6 to SLA0 GC SnADR.0 BIT SnADR.7 to SnADR.1 Own slave address When a logic 0, the general call address is not recognized. When a logic 1, the general call address is recognized FUNCTION August 1993 45 Philips Semiconductors Product specification 16-bit microcontroller 8.2.5 INTERRUPT REGISTERS P90CE201 The interface contains four registers for the control of I2C-bus interrupts. One pair of registers (S1IR and S1IV) provide independent control of the I2C1 interface interrupts; the other pair of registers (S2IR and S2IV) provide independent control of the I2C2 interface interrupts. In the following register descriptions "n" represents the I2C-bus interface number (1 or 2), its associated registers are identified using the same number. 8.2.6 INTERRUPT REGISTERS (SnIR) I2C-bus These registers have a default value of XX0X0000b. bit 7 - bit 6 - bit 5 AVN bit 4 - bit 3 PIR bit 2 IPL2 bit 1 IPL1 bit 0 IPL0 Fig.29 Interrupt Register (SnIR). Table 39 Description of SnIR bits. SYMBOL - - AVN BIT SnIR.7 SnIR.6 SnIR.5 Reserved Reserved Autovector. When AVN = 0; the interrupt is an autovectored interrupt and the processor calculates the appropriate vector from a fixed vector table. AVN = 0 is also the default value. When AVN = 1; the interrupt is a vectored interrupt and the peripheral must provide an 8-bit vector number. Reserved Pending Interrupt Request. This bit is set to a logic 1 when a valid interrupt request has been detected. It is automatically reset by the interrupt acknowledge cycle from the CPU. If PIR = 0, there is no pending interrupt request; this is also the default value. The PIR bit can also be reset by software by writing a logic 0 to this location. Interrupt Priority Level. These three bits select the interrupt priority level. See Table 40. FUNCTION - PIR SnIR.4 SnIR.3 IPL2 IPL1 IPL0 SnIR.2 SnIR.1 SnIR.1 Table 40 Selection of interrupt priority level. IPL2 0 0 0 0 1 1 1 1 IPL1 0 0 1 1 0 0 1 1 IPL0 0 1 0 1 0 1 0 1 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 PRIORITY LEVEL Interrupt inhibited; this is also the default value. August 1993 46 Philips Semiconductors Product specification 16-bit microcontroller 8.2.7 INTERRUPT VECTOR (SnIV) P90CE201 These registers have a default value of 0FH. bit 7 IV.7 bit 6 IV.6 bit 5 IV.5 bit 4 IV.4 bit 3 IV.3 bit 2 IV.2 bit 1 IV.1 bit 0 IV.0 Fig.30 Interrupt Vector (SnIV). Table 41 Description of SnIV bits. SYMBOL IV.7 to IV.0 BIT SnIV.7 to SnIV.0 FUNCTION 8-bit interrupt vector number. The default value of this register is 0FH. August 1993 47 Philips Semiconductors Product specification 16-bit microcontroller 9 9.1 UART SERIAL INTERFACE General Mode 2: P90CE201 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCON) usually represents the parity bit. On receive, the 9th data bit is stored in RB8 in SCON, while the stop bit is ignored. The baud rate is fixed at 3/32 of the BPCLK frequency. 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (1). Mode 3 is the same as Mode 2 except that the baud rate in Mode 3 is variable. This serial port is full duplex which means that it can transmit and receive simultaneously. It is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the receive register. (However, if the first byte has not been read by the time the reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed as register SBUF. Writing to SBUF loads the Transmit Register and reading SBUF accesses the physically separate Receive Register. The baud rate for receiver and transmitter can be generated by any timer using its baud rate generator output. 9.2 Operating modes The serial port can operate in one of four modes: Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. 8 data bits are transmitted or received (LSB first). The baud rate is fixed at 1/4 the basic peripheral clock. 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit is stored in RB8 in register SCON. The baud rate is variable. Mode 3: In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. Mode 1: 9.3 9.3.1 UART registers UART SHIFT REGISTER (SBUF) The UART Shift Register resides at address 8000 2021H. SBUF contains the serial data to be transmitted or data just being received. Bit 0 is transmitted or received first; i.e data is shifted from left to right. bit 7 SBUF.7 bit 6 SBUF.6 bit 5 SBUF.5 bit 4 SBUF.4 bit 3 SBUF.3 bit 2 SBUF.2 bit 1 SBUF.1 bit 0 SBUF.0 Fig.31 UART Shift Register (SBUF). August 1993 48 Philips Semiconductors Product specification 16-bit microcontroller 9.3.2 UART CONTROL REGISTER (SCON) P90CE201 The Serial Port Control Register and Status Register (SCON) contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). SCON has a default value of 00H. bit 7 SM0 bit 6 SM1 bit 5 SM2 bit 4 REN bit 3 TB8 bit 2 RB8 bit 1 TI bit 0 RI Fig.32 UART Control Register (SCON). Table 42 Description of SCON bits. SYMBOL SM0 SM1 SM2 BIT SCON.7 SCON.6 SCON.5 FUNCTION These two bits are used to select the serial port mode. See Table 43. Enables the multiprocessor communication feature in Modes 2 and 3. In Modes 2 and 3, if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be a logic 0. Enables serial reception and is set by software to enable reception, and cleared by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as required. In Modes 2 and 3, RB8 is the 9th data bit that is received. In Mode 1, if SM2 = 0, then RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. Must be cleared by software. Receive Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (however see SM2). Must be cleared by software. REN TB8 RB8 TI SCON.4 SCON.3 SCON.2 SCON.1 RI SCON.0 Table 43 Selection of the serial port modes. SM0 0 0 1 1 SM1 0 1 0 1 MODE 0 1 2 3 DESCRIPTION Shift register 8-bit UART 9-bit UART 9-bit UART BAUD RATE BPCLK/4 variable 3/32 BPCLK variable August 1993 49 Philips Semiconductors Product specification 16-bit microcontroller 9.3.3 UART INTERRUPT REGISTERS P90CE201 The UART interface contains four registers for the control of the transmitter and receiver interrupts. One pair of registers (UTIR and UTIV) provide independent control of transmitter interrupts; the other pair of registers (URIR and URIV) provide independent control of receiver interrupts. In the following register descriptions "x" can be replaced by "T" for transmitter, or "R" for receiver. 9.3.4 UART TRANSMITTER/RECEIVER INTERRUPT REGISTER (UXIR) These registers have a default value of XX0X0000b. bit 7 - bit 6 - bit 5 AVN bit 4 - bit 3 PIR bit 2 IPL2 bit 1 IPL1 bit 0 IPL0 Fig.33 UART Transmitter/Receiver Interrupt Register (UxIR). Table 44 Description of UxIR bits. SYMBOL - - AVN BIT UxIR.7 UxIR.6 UxIR.5 Reserved Reserved Autovector. When AVN = 0; the transmitter/receiver interrupt is an autovectored interrupt and the processor calculates the appropriate vector from a fixed vector table. AVN = 0 is also the default value. When AVN = 1; the transmitter/receiver interrupt is a vectored interrupt and the peripheral must provide an 8-bit vector number. Reserved Pending Interrupt Request. This bit is set to a logic 1 when a valid interrupt request has been detected. It is automatically reset by the interrupt acknowledge cycle from the CPU. If PIR = 0; there is no pending interrupt request; this is also the default value. PIR can be reset by software by writing a logic 0 to this location. Interrupt Priority Level. These three bits determine the interrupt priority level of the interrupt requested by the transmitter/receiver. See Table 45. FUNCTION - PIR UxIR.4 UxIR.3 IPL2 IPL1 IPL0 UxIR.2 UxIR.1 UXIR.0 August 1993 50 Philips Semiconductors Product specification 16-bit microcontroller Table 45 Selection of transmitter/receiver interrupt priority level. IPL2 0 0 0 0 1 1 1 1 9.3.5 IPL1 0 0 1 1 0 0 1 1 IPL0 0 1 0 1 0 1 0 1 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 PRIORITY LEVEL Interrupt inhibited; this is also the default value. P90CE201 UART TRANSMITTER/RECEIVER INTERRUPT VECTOR (UXIV) These registers have a default value of 0FH. bit 7 IV.7 bit 6 IV.6 bit 5 IV.5 bit 4 IV.4 bit 3 IV.3 bit 2 IV.2 bit 1 IV.1 bit 0 IV.0 Fig.34 UART Transmitter/Receiver Interrupt Vector (UxIV). Table 46 Description of UxIV bits. SYMBOL IV.7 to IV.0 BIT UTIV.7 to UTIV.0 FUNCTION 8-bit interrupt vector number. The default value of this register is 0FH. August 1993 51 Philips Semiconductors Product specification 16-bit microcontroller 10 8-BIT GENERAL PORT The port is configured as a quasi-bidirectional port. A port pin is set to input mode by writing a logic 1 to the corresponding General Port Register (GP) bit. This drives a "hard" logic 1 to the corresponding output pin for a short period. After this period the logic 1 level is maintained by a weak pull-up transistor, which can be overwritten by an external signal. A read from GP reads the value from the corresponding General Port Register bit. A read from the General Port Pad/Register (GPP) reads the value from the corresponding port input pin. A write to either GP or GPP writes the value to the port register (GP) from where it is driven to the corresponding port pins. After RESET the port is set to input mode. Bits 0 to 3 can be used as high current drive outputs at a logic 0. Bits 6 and 7 may also be used for I2C1 and therefore no internal pull-ups are implemented. 10.1 10.1.1 8-bit General Port registers GENERAL PORT REGISTER (GP) P90CE201 This register is located at address 8000 2073H. bit 7 GP7 bit 6 GP6 bit 5 GP5 bit 4 GP4 bit 3 GP3 bit 2 GP2 bit 1 GP1 bit 0 GP0 Fig.35 General Port Register (GP). 10.1.2 GENERAL PORT PAD/REGISTER (GPP) This register is located at address 8000 2071H. bit 7 GPP7 bit 6 GPP6 bit 5 GPP5 bit 4 GPP4 bit 3 GPP3 bit 2 GPP2 bit 1 GPP1 bit 0 GPP0 Fig.36 General Port Pad/Register (GPP). August 1993 52 Philips Semiconductors Product specification 16-bit microcontroller 11 8-bit AUXILIARY PORT Unused address pins can be used as auxiliary ports. The selection of unused address pins (A23 to A16) for use as auxiliary ports is controlled by the Auxiliary Port Control Register (APCON). Each bit in APCON controls one address pin. A logic 1 written to APCON.n enables the auxiliary port function of the address pin A(n + 16). The APCON bits and their associated address pins are shown in Fig.37. A logic 0 written to APCON.n disables the auxiliary port function and drives the internal address bus to A(n + 16). If bit APCON.n is set, a read from the corresponding bit APP.n in the Auxiliary Port Pad/Register (APP), reads the value from the address pin A(n + 16). A write to APP.n when APCON.n is set, drives the value of APP.n to the address pin A(n + 16). After RESET the auxiliary port function is disabled (APCON = 00H). 11.1 11.1.1 8-bit Auxiliary Port registers AUXILIARY PORT CONTROL REGISTER (APCON) P90CE201 The Auxiliary Port is configured as a quasi-bidirectional port in the same way as described for the 8-bit General Port. A port pin is set to input mode by writing a logic 1 to the corresponding port register bit. This drives a "hard" logic 1 to the corresponding output pin for a short period. After this period the logic 1 level is maintained by a weak pull-up transistor, which can be overwritten by an external signal. This register is located at address 8000 2083H. bit 7 APCON.7 (A23) bit 6 APCON.6 (A22) bit 5 APCON.5 (A21) bit 4 APCON.4 (A20) bit 3 APCON.3 (A19) bit 2 APCON.2 (A18) bit 1 APCON.1 (A17) bit 0 APCON.0 (A16) Fig.37 Auxiliary Port Control Register (APCON). 11.1.2 AUXILIARY PORT PAD/REGISTER (APP) This register is located at address 8000 2081H. bit 7 APP7 bit 6 APP6 bit 5 APP5 bit 4 APP4 bit 3 APP3 bit 2 APP2 bit 1 APP1 bit 0 APP0 Fig.38 Auxiliary Port/Pad Register (APP). August 1993 53 Philips Semiconductors Product specification 16-bit microcontroller 12 WATCHDOG TIMER The P90CE201 contains a Watchdog Timer. Its purpose is to reset the microcontroller, after a programmable time interval, in the event of the microcontroller entering an erroneous processor state. Erroneous processor states can be caused by noise or RFI. The Watchdog Timer consists of a 14-bit prescaler and an 8-bit timer (WDTIM). The prescaler is incremented by the basic peripheral clock. WDTIM is incremented every 16384 cycles of the basic peripheral clock. It is the value written to WDTIM that determines the Watchdog Timer interval. If the timer interval is exceeded, the Watchdog Timer overflows and the microcontroller is reset. In order to prevent a timer overflow, the user program must reload the Watchdog Timer within a time period shorter than the programmed Watchdog Timer interval. The Watchdog Timer is controlled by the Watchdog Control Register (WDCON). WDCON can be read and P90CE201 written to by software. After RESET, the Watchdog Timer is disabled and WDCON contains A5H which clears both the prescaler and WDTIM. The Watchdog Timer is enabled by the first write operation to WDCON after RESET. A running Watchdog Timer can only be disabled by resetting the device. WDTIM can be read on the fly but can only be written to if WDCON has been loaded with 5AH. A successful write operation to WDTIM also clears the prescaler and sets WDCON to 00H in order to prevent further, unintentional, write operations to WDTIM. The Watchdog Timer interval (t) may be calculated as ( 256 - WDTIM value ) x 16384 follows: t = -------------------------------------------------------------------------------------basic peripheral clock frequency For example, if the basic peripheral clock frequency is 4 MHz, the Watchdog Timer interval will be within the range 4.1 ms to 1 second. handbook, full pagewidth INTERNAL BUS BPCLK PRESCALER (14-BIT) CLEAR CLEAREN WDTIM (8-BIT) LOAD LOADEN to reset circuitry CLEAR write WDTIM WDCON from reset circuitry INTERNAL BUS MLB253 Fig.39 Watchdog Timer. August 1993 54 Philips Semiconductors Product specification 16-bit microcontroller 13 TIMERS 13.1 General 13.2 Timer operating modes P90CE201 The P90CE201 contains three almost identical, fully independent 16-bit timers (T0, T1 and T2). In the following general description of the timer block, "n" represents the number of the Timer (0, 1 or 2). Timer n is a 16-bit timer/counter which is formed by the two 8-bit registers TLn and THn. Another pair of registers, RCAPLn and RCAPHn, form a 16-bit capture register or a 16-bit reload register. The timers can operate either as a timer or as an event counter. The selection of the clock source for each timer is done in register SYSCON2 (see Table 12). The timers have three operation modes. Mode 1: Mode 2: mode 3: Timer/counter in capture mode Timer/counter in auto-reload mode Timer/counter in baud rate generator mode for UART The Timer Control Register (TnCON) controls the selection of the timer operating modes; this is described in section 13.3.1 Timer Control Register (TnCON). 13.2.1 CAPTURE MODE In the Capture mode there are two options which are selected by the EXENn bit in TnCON. If EXENn = 0, then Timer n is a 16-bit timer/counter which on overflow sets the Overflow bit TFn. The overflow can be used to generate an interrupt. If EXENn = 1, then Timer n operates in the same way as EXENn = 0 but with the additional feature that a valid transition at the external input Tn causes the current value in Timer n registers (TLn and THn) to be captured into registers RCAPLn and RCAPHn, respectively. The transition at input Tn also causes the EXFn bit in TnCON to be set; this can also be used to generate an interrupt. 13.2.2 AUTO-RELOAD MODE The differences between the three timers are listed below: Timer 0: Operates in all modes with the internal frequency of fXTAL/2 or fXTAL/32. Timer 0 contains a transition detection circuit for the external input. The detection circuitry is controlled by two bits in SYSCON2; all possible transitions can be monitored. Table 47 shows the selection of the trigger pulse. In the Auto-reload mode there are two options which are selected by the EXENn bit in TnCON. If EXENn = 0, then a Timer n overflow sets the TFn bit and causes the Timer n registers to be reloaded with the 16-bit value held in registers RCAPLn and RCAPHn. This 16-bit value is preset by software. The overflow can be used to generate an interrupt. If EXENn = 1, then Timer n operates as above but with the additional feature that a valid transition at the external input Tn triggers the 16-bit reload and sets the EXFn bit. The transition can also be used to generate an interrupt. 13.2.3 BAUD RATE GENERATOR MODE Table 47 Selection of the trigger pulse. SYSCON2.3 0 0 1 1 SYSCON2.2 0 1 0 1 TRANSITION no edge detection rising edge detection falling edge detection (default value) falling and rising edge detection Timer 1: Operates in all modes with the internal frequency of fXTAL/2 or fXTAL/32. Transition detection for the external input is fixed to falling edge detection. Operates in all modes with the internal frequency of fXTAL/2 or BPCLK/4. Transition detection for the external input is fixed to falling edge detection. The baud rate generator mode for the UART is selected by RCLKn and/or TCLKn in TnCON. Overflows of Timer n can be used or generating baud rates for transmit and receive of the UART in its Modes 1 and 3. See Table 50. The baud rate generation mode is similar to the auto-reload mode, in that a rollover in THn causes the Timer n registers to be reloaded with the 16-bit value held in registers RCAPLn and RCAPHn, which are preset by software. The baud rate for the UART is determined by Timer n's overflow rate as specified below. Timer n overflow rate Baud rate = --------------------------------------------------------16 Timer 2: August 1993 55 Philips Semiconductors Product specification 16-bit microcontroller Timer n can be configured for either timer or counter operation. In timer operation the internal timer frequency (fINT) is given by fXTAL/2, fXTAL/32 or BPCLK/4. The baud rate may be calculated as follows: f INT Baud rate = -----------------------------------------------------------------------------------------------------16 x ( 65536 - ( RCAPnH, RCAPnL ) ) In this mode an overflow of Timer n does not set TFn and does not generate an interrupt. If EXENn = 1, a valid transition at input pin Tn sets EXFn and can be used to generate an interrupt. P90CE201 handbook, full pagewidth OSC PRESCALER C/Tn = 0 TLn (8 BITS) C/Tn = 1 control TRn capture timer n interrupt RCAPnL RCAPnH THn (8 BITS) TFn transition detector external pin Tn control EXENn EXFn MLB008 Fig.40 Timer/Counter in Capture Mode - Mode 1. August 1993 56 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 handbook, full pagewidth OSC PRESCALER C/Tn = 0 TLn (8 BITS) C/Tn = 1 control TRn reload timer n interrupt RCAPnL RCAPnH THn (8 BITS) TFn transition detector external pin Tn control EXENn EXFn MLB009 Fig.41 Timer/Counter in Auto-reload Mode - Mode 2. handbook, full pagewidth OSC PRESCALER C/Tn = 0 TLn (8 BITS) C/Tn = 1 control TRn reload UART clock timer n interrupt RCAPnL RCAPnH THn (8 BITS) transition detector external pin Tn control EXENn EXFn MLB010 Fig.42 Timer/Counter in Baud rate generator Mode - Mode 3. August 1993 57 Philips Semiconductors Product specification 16-bit microcontroller 13.3 13.3.1 Timer registers TIMER CONTROL REGISTER (TnCON) P90CE201 The Timer Control Register (TnCON) controls the selection of the timer operating modes and the UART clock source. bit 7 TFn bit 6 EXFn bit 5 RCLKn bit 4 TCLKn bit 3 EXENn bit 2 TRn bit 1 C/Tn bit 0 CP/RLn Fig.43 Timer Control Registers (TnCON). Table 48 Description of TnCON bits. SYMBOL TFn EXFn BIT TnCON.7 TnCON.6 FUNCTION Timer n overflow flag. Set by a Timer n overflow and must be cleared by software. TFn will not be set when either RCLKn = 1 or TCLKn = 1. Timer n external flag. Set when either a capture or reload is caused by a negative transition on external input Tn and when EXENn = 1. EXFn must be cleared by software. Receive Clock flag. When set, causes the UART to use Timer n overflow pulses for its receive clock in Modes 1 and 3. See Table 50. Transmit Clock flag. When set, causes the UART to use Timer n overflow pulses for its transmit clock in Modes 1 and 3. See Table 50. Timer n external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on external input Tn, if Timer n is not being used to clock the UART. EXENn = 0 causes Timer 2 to ignore events at external input Tn. Start/Stop control. TRn = 1 starts Timer n; TRn = 0 stops the timer. Timer or Counter select. C/Tn = 0 selects the internal timer. C/Tn = 1 selects the external event counter (edge triggered). Capture/Reload flag. When set, captures will occur on valid transitions at external input Tn, if EXEn2 = 1. When cleared, auto-reloads will occur upon either Timer n overflows or valid transitions at Tn, if EXENn = 1. When either RCLKn = 1 or TCLKn = 1, this bit is ignored and the timer is forced to auto-reload on a Timer n overflow. RCLKn TCLKn EXENn TnCON.5 TnCON.4 TnCON.3 TRn C/Tn CP/RLn TnCON.2 TnCON.1 TnCON.0 August 1993 58 Philips Semiconductors Product specification 16-bit microcontroller Table 49 Selection of Timer n operating modes. RCLKn + TCLKn 0 0 1 X CP/RLn 0 1 X X TRn 1 1 1 0 16-bit automatic reload 16-bit capture Baud rate generator off MODE P90CE201 Table 50 UART clock source for Receive and Transmit - Modes 1 and 3. RCLK2 TCLK2 0 0 0 1 X 1 1 Note 1. These combinations lead to the addition of clock pulses from different timers giving an irregular baud rate clock and therefore should not be used. RCLK1 TCLK1 0 0 1 0 1 X 1 RCLK0 UART CLOCK SOURCE TCLK0 0 1 0 0 1 1 X None Timer 0 Timer 1 Timer 2 Not usable, see note 1 Not usable, see note 1 Not usable, see note 1 August 1993 59 Philips Semiconductors Product specification 16-bit microcontroller 13.3.2 TIMER INTERRUPT REGISTER (TnIR) P90CE201 Each Timer contains a register for the control of interrupts. bit 7 - bit 6 - bit 5 AVN bit 4 - bit 3 PIR bit 2 IPL2 bit 1 IPL1 bit 0 IPL0 Fig.44 Timer Interrupt Register (TnIR). Table 51 Description of TnIR bits. SYMBOL - - AVN BIT TnIR.7 TnIR.6 TnIR.5 Reserved Reserved Autovector. When AVN = 0; the timer interrupt is an autovectored interrupt and the processor calculates the appropriate vector from a fixed vector table. AVN = 0 is also the default value. When AVN = 1; the timer interrupt is a vectored interrupt and the peripheral must provide an 8-bit vectored interrupt. Reserved Pending Interrupt Request. This bit is set to a logic 1 when a valid interrupt request has been detected. It is automatically reset by the interrupt acknowledge cycle from the CPU. If PIR = 0, there is no pending interrupt request; this is also the default value. The PIR bit can be reset by software by writing a logic 0 to this location. Interrupt Priority Level. These three bits determine the interrupt priority level of the interrupt requested by the timer. See Table 52. FUNCTION - PIR TnIR.4 TnIR.3 IPL2 IPL1 IPL0 TnIR.2 TnIR.1 TnIR.0 Table 52 Selection of interrupt priority level. IPL2 0 0 0 0 1 1 1 1 IPL1 0 0 1 1 0 0 1 1 IPL0 0 1 0 1 0 1 0 1 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 PRIORITY LEVEL Interrupt inhibited; this is also the default value. August 1993 60 Philips Semiconductors Product specification 16-bit microcontroller 13.3.3 TIMER INTERRUPT VECTOR (TnIV) bit 7 IV.7 bit 6 IV.6 bit 5 IV.5 bit 4 IV.4 bit 3 IV.3 bit 2 IV.2 bit 1 IV.1 P90CE201 bit 0 IV.0 Fig.45 Interrupt Vector Register (TnIV). Table 53 Description of TnIV bits. SYMBOL IV.7 to IV.0 BIT TnIV.7 to TnIV.0 FUNCTION 8-bit interrupt vector number. The default value of this register is 0FH. August 1993 61 Philips Semiconductors Product specification 16-bit microcontroller 14 ELECTROMAGNETIC COMPATIBILITY (EMC) IMPROVEMENTS P90CE201 Primary attention has been paid to the reduction of electromagnetic emission of the microcontroller. The following features result in a reduction of the electromagnetic emission and additionally improve the electromagnetic susceptibility: * Two supply voltage pins (VDD1 and VDD2) and two ground pins (VSS1 and VSS2) are provided. VDD1 and VSS1 are adjacent pins located on one side of the package; VDD2 and VSS2 are also adjacent pins located diagonally opposite the VDD1 and VSS1 pins. * Separate power supply pins for internal logic/memory interface and peripheral pins (quiet port) * Internal decoupling capacitance improves the EMC radiation behaviour and the EMC immunity * External capacitors are to be connected as close as possible between pins VDD1 and VSS1 and also VDD2 and VSS2. Ceramic chip capacitors are recommended (100 nF). 15 ELECTRICAL SPECIFICATIONS 15.1 Limiting values In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI Ptot Tstg Tamb Note 1. This value is based on the maximum allowable die temperature and the thermal resistance of the package; not on device power consumption. supply voltage input voltage on any pin with respect to ground (VSS) total power dissipation; see note 1 storage temperature operating ambient temperature PARAMETER MIN. -0.5 -0.5 - -65 -25 MAX. +6.5 VDD + 0.5 0.75 +150 + 85 UNIT V V W C C August 1993 62 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 15.2 DC Characteristics VDD = 5 V 10%; VSS = 0 V; Tamb = -25 to +85 C; all voltages with respect to VSS unless otherwise specified. SYMBOL Supply VDD IDD RRST Inputs VIL VIL1 VIH LOW level input voltage (except SCLn and SDAn) LOW level input voltage SCLn and SDAn HIGH level input voltage (except RESET, XTAL1, SCLn, SDAn) HIGH level input voltage RESET, XTAL1 HIGH level input voltage SCLn, SDAn LOW level input current GP0-5, A16-23 in port mode, INTN0 - 7 input current HIGH-to-LOW transition for externally driven port pins (except GP6 and GP7) input leakage current D0 to D7 input leakage current SCLn, SDAn note 2 VIN = 0.45 V note 2 -0.5 -0.5 2.0 0.8 1.5 VDD + 0.5 V V V supply voltage supply current operating RESET pull-down resistor VDD = 5.5 V; fCLK = 24 MHz note 1 4.5 - 50 5.5 70 150 V mA k PARAMETER CONDITIONS MIN. MAX. UNIT VIH1 VIH2 IIL 0.7VDD + 0.1 3.0 - VDD + 0.5 6.0 -50 V V A ITL VIN = 2.0 V - -650 A ILI ILI1 Outputs VOL VOL1 VOL2 VOH 0.45 V VIN VDD 0.4 V VIN 4.95 V note 2 - - 10 10 A A LOW level output voltage (except GP0-3, SCLn,SDAn) LOW level output voltage GP0-3 LOW level output voltage SCLn, SDAn HIGH level output voltage (except SCLn,SDAn) IOL = 1.6 mA; note 3 IOL = 6.4 mA; note 3 IIOL = 20 mA; note 3 IOL = 3.0 mA; notes 2 and 3 IOL = 60 mA; notes 2 and 3 IOH = -60 A - - - - 2.4 0.45 0.45 1.2 0.4 0.6 - V V V V V V August 1993 63 Philips Semiconductors Product specification 16-bit microcontroller Notes P90CE201 1. The operating supply current is measured during the STOP instruction executed immediately after RESET. All inputs are driven HIGH and outputs are loaded with CL = 50 pF, R = 1 M; XTAL1 is driven with tr = tf = 5 ns; VIL = VSS + 0.5 V; VIH1 = VDD - 0.5 V; XTAL2 not connected. 2. The parameter meets the I2C-bus specification for standard mode and fast mode devices. 3. Under steady state (non-transient) conditions, IOL must be externally limited as shown in Table 54. If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. Table 54 Maximum IOL values. PARAMETER Maximum IOL per port pin Maximum IOL per high drive port pin (GP0 - GP3) Maximum total IOL for all output pins 15.3 AC Characteristics MAX 10 20 100 UNIT mA mA mA VDD = 5 V 10%; VSS = 0 V; TCLCLmin = 1/fCLKmax = 42 ns; Tamb = -25 to +85 C. 15.3.1 AC TESTING INPUT AND OUTPUT WAVEFORMS. AC test inputs are driven at 2.4 V for a logic 1 and 0.45 V for a logic 0. Timing measurements are taken at 2.0 V for a logic 1 and 0.8 V for a logic 0. See Fig.46(a). The float state is defined as the point at which the pin sinks 3.2 mA or sources 400 A at the voltage test levels. See Fig.46(b). 2.0 V handbook, full pagewidth 2.0 V 2.4 V test points 0.45 V 0.8 V (a) float 0.8 V 2.4 V 2.0 V 0.8 V 2.0 V 0.8 V 0.45 V (b) MLA769 Fig.46 AC testing input, output waveform (a) and float waveform (b). August 1993 64 Philips Semiconductors Product specification 16-bit microcontroller 15.3.2 EXTERNAL CLOCK DRIVE XTAL1 P90CE201 Table 55 External clock drive XTAL1. SYMBOL tCLCL tCHCX tCLCX tCLCH tCHCL clock period HIGH time LOW time rise time fall time PARAMETER MIN. 42 15 15 - - 250 tCLCL - tCLCX tCLCL - tCHCX 20 20 MAX. UNIT ns ns ns ns ns handbook, full pagewidth t CHCX V IH1 0.8 V V IH1 0.8 V t CLCH V IH1 0.8 V t CLCX t CLCL V IH1 0.8 V t CHCL MLA856 Fig.47 External clock drive XTAL1. August 1993 65 Philips Semiconductors Product specification 16-bit microcontroller 15.3.3 EXTERNAL MEMORY INTERFACE P90CE201 Table 56 External memory read cycle timing. SYMBOL tAVSL tSLDV tAXDX tAVDV tSHAX tSHDX Note 1. WS is the number of additional wait states access time values. See Table 11 in section 6. PARAMETER address valid to CSROMN/CSRAMN LOW CSROMN/CSRAMN LOW to data valid; note 1 address invalid to data invalid address valid to data valid; note 1 CSROMN/CSRAMN HIGH to address invalid CSROMN/CSRAMN HIGH to data invalid - 0 - tCLCL - 15 0 MIN. tCLCL - 25 - (2 + WS/2)tCLCL - 65 - (2 + WS/2)tCLCL - 65 - - MAX. UNIT ns ns ns ns ns ns handbook, full pagewidth Address even address address 1 R/WN t AVSL CSRAMN CSROMN t SLDV D0 D7 MSB data t AXDX LSB data MLB013 t AVDV t SHAX t SHDX Fig.48 External memory read cycle. August 1993 66 Philips Semiconductors Product specification 16-bit microcontroller Table 57 External memory write cycle timing. SYMBOL tAVSL tWLSL tSHWH tSLSH tSHAX tQVSH tSHQX Note 1. WS is the number of additional wait states access time values. See Table 11 in section 6. PARAMETER address valid to CSROMN/CSRAMN LOW RWN LOW to CSROMN/CSRAMN LOW CSROMN/CSRAMN HIGH to RWN HIGH CSROMN/CSRAMN LOW; note 1 CSROMN/CSRAMN HIGH to address invalid data set-up to CSROMN/CSRAMN HIGH; note 1 CSROMN/CSRAMN HIGH to data invalid tCLCL - 25 tCLCL - 25 tCLCL - 15 (2 + WS/2)tCLCL - 15 tCLCL - 15 (2 + WS/2)tCLCL - 20 tCLCL - 15 MIN. P90CE201 UNIT ns ns ns ns ns ns ns handbook, full pagewidth Address MSB address t WLSL LSB address R/WN t AVSL CSRAMN CSROMN t QVSH D0 D7 MLB123 t SLSH t SHAX t SHWH t SHQX Fig.49 External memory write cycle. August 1993 67 Philips Semiconductors Product specification 16-bit microcontroller 15.3.4 FAST I2C-BUS TIMING. P90CE201 Table 58 Fast I2C-bus timing. SYMBOL fSCL tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tRC;tRD tFC;tFD tSU; STO Cb Notes 1. A device must internally provide a hold time of at least 300 ns for the SDA signal, referenced to VIHmin of the SCL signal, in order to bridge the undefined region of the falling edge of SCL. The maximum tHD;DAT has to be met only if the device does not stretch the SCL LOW period (tLOW). 2. A fast-mode I2C-bus device can be used in a "0-to-100 kbit/s" I2C-bus system and then the requirement tSU;DAT > 250 ns must be fulfilled. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. But if such a device stretches the LOW period of the SCL signal, it must output the next data bit to the SDA line (tRDmax + tSU;DAT) = 1000 + 250 = 1250 ns before the SCL line is released according to the existing "0-to-100 kbit/s" I2C-bus specification. 3. Cb = Total capacitance value of one bus line in pF. SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock set-up time (repeated) START data hold time (note 1) data set-up time (note 2) rise time of both SDA and SCL lines (note 3) fall time of both SDA and SCL lines (note 3) set-up time for STOP condition capacitive load of each bus line PARAMETER 0 1300 600 1300 600 600 0 100 (20 + 0.1Cb) (20 + 0.1Cb) 600 - MIN. MAX. 400 - - - - - 900 - 300 300 - 400 UNIT kHz ns ns ns ns ns ns ns ns ns ns pF August 1993 68 handbook, full pagewidth August 1993 Philips Semiconductors 16-bit microcontroller repeated START condition START condition STOP condition t RD t SU;STA START or repeated START condition SDA (input / output) t BUF t SU;STO 0.7 VDD 0.3 VDD t SU;DAT3 t SU;DAT2 0.7 V DD 0.3 VDD t FC 69 t HIGH t SU;DAT1 t HD;DAT t FD t RC SCL (input / output) t HD;STA t LOW MBC482 Product specification P90CE201 Fig.50 Fast I2C-bus interface timing. Philips Semiconductors Product specification 16-bit microcontroller 15.3.5 UART SHIFT REGISTER MODE TIMING P90CE201 Table 59 Basic peripheral clock set to 4 MHz; CL = 80 pF. SYMBOL tXLXL tQVXH tXHQX tXHDX tXHDV PARAMETER serial port clock cycle time output data set-up to clock rising edge output data hold after clock rising edge input data hold after clock rising edge clock rising edge to input data valid MIN. 1000 700 50 0 - MAX. - - - - 700 UNIT ns ns ns ns ns handbook, full pagewidth t XLXL CLOCK t XHQX t QVXH OUTPUT DATA 0 t XHDV VALID VALID VALID VALID VALID VALID VALID 1 2 t XHDX 3 4 5 6 7 WRITE TO SBUF INPUT DATA SET TI VALID CLEAR RI MLB124 SET RI Fig.51 UART Shift Register mode timing. August 1993 70 Philips Semiconductors Product specification 16-bit microcontroller 16 REGISTER MAP The internal register map of the P90CE201 is summarized in the following tables. ADDRESS (HEX) System registers 8000 1000 8000 1001 8000 1002 8000 1003 8000 1004 to 800 101F Interrupt registers 8000 1020 8000 1021 8000 1022 8000 1023 8000 1024 8000 1025 8000 1026 8000 1027 8000 1028 8000 1029 8000 102A 8000 102B 8000 102C 8000 102D 8000 102E 8000 102F 8000 1030 8000 1031 8000 1032 8000 1033 8000 1034 to 8000 1040 8000 1041 8000 1042 8000 1043 8000 1044 8000 1045 8000 1046 8000 1047 LIV2 LIR2 LIV3 LIR3 LPPH LPCRH LIV4 LIR4 LIV5 LIR5 LIV6 LIR6 LIV7 LIR7 Reserved Latched Interrupt 7 Register Reserved Latched Interrupt 7 vector Reserved Latched Interrupt 6 Register Reserved Latched Interrupt 6 vector Reserved Latched Interrupt 5 Register Reserved Latched Interrupt 5 vector Reserved Latched Interrupt 4 Register Reserved Latched Interrupt 4 vector Reserved Port Control Register bit 7 to 4 Reserved Port Pad/Control Register bit 7 to 4 Reserved Latched Interrupt 3 Register Reserved Latched Interrupt 3 vector Reserved Latched Interrupt 2 Register Reserved Latched Interrupt 2 vector SYSCON1H SYSCON1L SYSCON2H SYSCON1L SYSCON2 SYSCON1 System Control Register 1 High System Control Register 1 Low System Control Register 2 High System Control Register 2 Low Reserved SYMBOL REGISTER P90CE201 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W August 1993 71 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 ADDRESS (HEX) 8000 1048 8000 1049 8000 104A 8000 104B 8000 104C 8000 104D 8000 104E 8000 104F 8000 1050 8000 1051 8000 1052 8000 1053 8000 1054 to 8000 105F I2C Registers 8000 2000 8000 2001 8000 2002 8000 2003 8000 2004 8000 2005 8000 2006 8000 2007 8000 2008 8000 2009 8000 200A 8000 200B 8000 200C to 8000 2010 8000 2011 8000 2012 8000 2013 8000 2014 8000 2015 8000 2016 8000 2017 8000 2018 8000 2019 8000 201A 8000 201B 8000 201C to 8000 201F S2IV S2IR S2CON S2STA S2ADR S2DAT S1IV S1IR S1CON S1STA S1ADR S1DAT LPPL LPCRL LIV0 LIR0 LIV1 LIR1 SYMBOL Reserved REGISTER Latched Interrupt 1 Register Reserved Latched Interrupt 1 vector Reserved Latched Interrupt 0 Register Reserved Latched Interrupt 0 vector Reserved Port Control Register bit 3 to 0 Reserved Port Pad/Control Register bit 3 to 0 Reserved R/W R/W R/W R/W R/W R/W Reserved I2C1 Data Register Reserved I2C1 Address Register Reserved I2C1 Status Register Reserved I2C1 Control Register Reserved I2C1 Interrupt Register Reserved I2C1 Interrupt vector Reserved I2C2 Data Register Reserved I2C2 Address Register Reserved I2C2 Status Register Reserved I2C2 Control Register Reserved I2C2 Interrupt Register Reserved I2C2 Interrupt vector Reserved R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W August 1993 72 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 ADDRESS (HEX) UART registers 8000 2020 8000 2021 8000 2022 8000 2023 8000 2024 8000 2025 8000 2026 8000 2027 8000 2028 8000 2029 8000 202A 8000 202B 8000 202C to 8000 202F Timers registers 8000 2030 8000 2031 8000 2032 8000 2033 8000 2034 8000 2035 8000 2036 8000 2037 8000 2038 8000 2039 8000 203A to 800 203F 8000 2040 8000 2041 8000 2042 8000 2043 8000 2044 8000 2045 8000 2046 8000 2047 8000 2048 8000 2049 8000 204A to 8000 204F 8000 2050 8000 2051 TH2 TL2 T1IV T1IR T1CON TH1 TL0 RCAPH1 RCAPL1 T0IV T0IR T0CON TH0 TL0 RCAPH0 RCAPL0 UTIV UTIR URIV URIR SCON SBUF SYMBOL REGISTER Reserved UART Transmit/Receive Register Reserved UART Control Register Reserved UART Receiver Interrupt Register Reserved UART Receiver Interrupt vector Reserved UART Transmitter Interrupt Register Reserved UART Transmitter Interrupt vector Reserved R/W R/W R/W R/W R/W R/W T0 RCAP0 Timer 0 High Order Register Timer 0 Low Order Register Timer 0 Reload/Capture High Order Register Timer 0 Reload/Capture Low Order Register Reserved Timer 0 Control Register Reserved Timer 0 Interrupt Register Reserved Timer 0 Interrupt vector Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W T1 RCAP1 Timer 1 High Order Register Timer 1 Low Order Register Timer 1 Reload/Capture High Order Register Timer 1 Reload/Capture Low Order Register Reserved Timer 1 Control Register Reserved Timer 1 Interrupt Register Reserved Timer 1 Interrupt vector Reserved T2 Timer 2 High Order Register Timer 2 Low Order Register August 1993 73 Philips Semiconductors Product specification 16-bit microcontroller P90CE201 ADDRESS (HEX) 8000 2052 8000 2053 8000 2054 8000 2055 8000 2056 8000 2057 8000 2058 8000 2059 8000 205A to 8000 205F Watchdog registers 8000 2060 8000 2061 8000 2062 8000 2063 8000 2064 to 8000 206F General Port registers 8000 2070 8000 2071 8000 2072 8000 2073 8000 2074 to 8000 207F Auxiliary Port registers 8000 2080 8000 2081 8000 2082 8000 2083 8000 2084 to 8000 208F APCON APP GP GPP WDCON WDTIM T2IV T2IR T2CON RCAPH2 RCAPL2 SYMBOL RCAP2 REGISTER Timer 2 Reload/Capture Low Order Register Timer 2 Reload/Capture Low Order Register Reserved Timer 2 Control Register Reserved Timer 2 Interrupt Register Reserved Timer 2 Interrupt vector Reserved R/W R/W R/W R/W R/W Reserved Watchdog Timer Register Reserved Watchdog Control Register Reserved R/W R/W Reserved Port Pad/Register Reserved Port Register Reserved R/W R/W Reserved Auxiliary Port Pad/Register Reserved Auxiliary Port Control Register Reserved R/W R/W August 1993 74 Philips Semiconductors Product specification 16-bit microcontroller 17 PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm P90CE201 SOT319-2 c y X 51 52 33 32 ZE A e E HE A A2 A1 (A 3) Lp bp 64 1 wM D HD ZD B vM B 19 vMA 20 detail X L pin 1 index wM e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 August 1993 75 Philips Semiconductors Product specification 16-bit microcontroller 18 SOLDERING 18.1 Introduction P90CE201 If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Repairing soldered joints There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 18.2 Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 18.3 Wave soldering Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. August 1993 76 Philips Semiconductors Product specification 16-bit microcontroller 19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values P90CE201 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. August 1993 77 |
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